An RF MOSFET includes respective pluralities of gate fingers, source fingers, and drain fingers formed on a semiconductor structure. The gate fingers are spaced apart from each other along a first direction, extend in a second, orthogonal direction, and are electrically connected to one another through a gate mandrel. The source fingers are spaced apart from each other along the first direction, extend in the second direction, and are electrically connected to one another through a source mandrel. The drain fingers are spaced apart from each other along the first direction, extend in the second direction, and are electrically connected to one another through a drain mandrel. Adjacent unit cell transistors of the RF MOSFET are separated from one another by a dummy gate and a trench that extends into the semiconductor structure. The semiconductor structure may be a bulk semiconductor wafer, a PD-SOI wafer, or an FD-SOI wafer.

A chip packaging structure includes a miniature antenna, an radio frequency identification chip, and a packaging member, wherein the radio frequency identification chip is electrically connected to the miniature antenna, and the packaging member is adapted to encapsulate the miniature antenna and the radio frequency identification chip, and has a top surface, a bottom surface, and a plurality of side surfaces, wherein the top surface, the bottom surface, and the side surfaces substantially form a hexahedron.

An electronic device includes a substrate, a bump, a chip, and an adhesive layer. The substrate includes a first connection pad. The bump is disposed on the first connection pad. The chip includes a second connection pad. The bump is disposed between the first connection pad and the second connection pad. The adhesive layer is disposed between the substrate and the chip. A dissipation factor of the adhesive layer is less than or equal to 0.01 at a frequency of 10 GHz. A manufacturing method of an electronic device includes the following: providing a substrate, where the substrate includes a first connection pad; applying an adhesive layer on the substrate; patterning the adhesive layer, such that the adhesive layer produces an opening exposing the first connection pad; forming a bump on the first connection pad; and bonding the chip onto the bump through the second connection pad.

A semiconductor package includes; a package substrate, a semiconductor chip on the package substrate, an electromagnetic shield structure on the package substrate and including an upper cover covering an upper surface of the semiconductor chip and a side cover surrounding the semiconductor chip, and a sealing member contacting the semiconductor chip and the electromagnetic shield structure, wherein the side cover includes first through holes and the upper cover includes second through holes.

The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.

An interconnect structure for insertion loss reduction in signal transmission and a method thereof are disclosed. In an embodiment, an interconnect is formed on a substrate by chemical etching process, and when the interconnect is protected by photoresist in chemical etching process, the etching direction of etching solution is not oriented, so undercut areas are respectively formed on both sides of a bottom of the interconnect at contact of the interconnect and the substrate because of etching solution residue after the etching process. An included angle formed in the undercut area between the interconnect and the substrate is defined as an etch angle, and a length of the portion, exposing in the undercut area, of the substrate is defined as an etch length. Controlling sizes of the etch angle and the etch length can reduce an insertion loss in signal transmission.

An electronic device and method is disclosed. In one example, the electronic device includes an electrically insulating material, a first load electrode arranged on a first surface of the electrically insulating material, and a second load electrode arranged on a second surface of the electrically insulating material opposite to the first surface, wherein the load electrodes are separated by the electrically insulating material along the entire length on which the load electrodes have opposite sections, wherein surfaces of the load electrodes facing away from the electrically insulating material are uncovered by the electrically insulating material.

Radio frequency (RF) packages containing multilevel power substrates and associated fabrication methods are disclosed. In an embodiment, the method includes producing a multilevel substrate panel by obtaining a base panel level containing prefabricated base structures and having a surface through which metallic surfaces of the prefabricated base structures are exposed. A secondary panel level is formed on the base layer to include patterned metal features embedded in a secondary dielectric body and electrically contacting the exposed metallic surfaces of the prefabricated base structures at a direct plated interface. The presingulated array of multilevel power substrates is separated into singulated multilevel power substrates each including a base substrate level formed from a singulated piece of the base panel level and a secondary substrate level formed from a singulated piece of the secondary substrate level.

An apparatus is described. The apparatus includes a semiconductor chip package substrate having a transmission line. The transmission line has a conductor to conduct current of a signal that is propagated along the transmission line. The conductor has an expanding width as the conductor approaches a vertical transition region. The vertical transition region is between the conductor and a solder ball. The transition region has multiple conducting vias at a same layer of the substrate. The multiple conducting vias are electrically connected to the conductor. The multiple conducting vias are radially arranged around a center axis of the solder ball.

The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.