Illustrative impedance matching circuits and methods provide enhanced performance without meaningfully increasing cost or areal requirements. One illustrative integrated circuit embodiment includes: a pin configured to connect to a substrate pad via a solder bump having a parasitic capacitance; an inductor that couples the pin to a transmit or receive circuit; a first electrostatic discharge (ESD) protection device electrically connected to a pin end of the inductor; and a second ESD protection device electrically connected to a circuit end of the inductor, where the first ESD protection device has a first capacitance that sums with the parasitic capacitance to equal a total capacitance coupled to the circuit end of the inductor.

An electronic device and method is disclosed. In one example, the electronic device includes an electrically insulating material, a first load electrode arranged on a first surface of the electrically insulating material, and a second load electrode arranged on a second surface of the electrically insulating material opposite to the first surface, wherein the load electrodes are separated by the electrically insulating material along the entire length on which the load electrodes have opposite sections, wherein surfaces of the load electrodes facing away from the electrically insulating material are uncovered by the electrically insulating material.

A phase-change material (PCM) switching device includes: a base dielectric layer over a semiconductor substrate; a first heater element disposed on the base dielectric layer, the first heater element comprising a first metal element characterized by a first coefficient of thermal expansion (CTE); a second heater element disposed on the first heater element, the second heater element comprising a second metal element characterized by a second CTE larger than the first CTE; a first metal pad and a second metal pad; and a PCM region comprising a PCM operable to switch between an amorphous state and a crystalline state in response to heat generated by the first heater element and the second heater element, wherein the PCM region is disposed above a top surface of the second heater element, and an air gap surrounds the first heater element and the second heater element from three sides.

A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.

A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.

The object is to provide a technology that can prevent a spring electrode from being dissolved and broken upon a short circuit in a semiconductor chip. A spring electrode includes a main body. The main body is a tubular conductor, and varies in diameter in a longitudinal direction so that a side surface has bellows. Since the main body of the spring electrode does not include an edge portion, the local concentration of a short-circuit current that flows through the spring electrode upon a short circuit in a semiconductor chip can be reduced. This can prevent the spring electrode from being dissolved and broken.

A high-frequency module 1 includes a component 3a mounted on an upper surface 2a of a substrate 2, a second sealing resin layer 4 stacked on the upper surface 2a of the substrate 2, a component 3b mounted on a lower surface 2b of the substrate 2, a first sealing resin layer 5 stacked on the lower surface 2b of the substrate 2, and a first terminal assembly 6 and a second terminal assembly 7 that are mounted on the lower surface 2b of the substrate 2. The first terminal assembly 6 is mounted on a four-corner portion of the substrate 2 and includes a connection conductor 6a thicker than a connection conductor 7a of the second terminal assembly 7.

A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.

Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.