An integrated circuit (IC) including a first transceiver interface circuit extending longitudinally in a first direction substantially perpendicular to a second direction parallel to edge of the IC, wherein the first transceiver interface circuit comprises a first T-coil; and a second transceiver interface circuit extending longitudinally in the first direction, wherein the second transceiver interface circuit is staggered from the first transceiver interface circuit along the second direction, wherein the second transceiver interface circuit includes a second T-coil, and wherein the second T-coil is offset from the first T-coil along the first direction.

An electronic package includes: a carrier structure; a first electronic component disposed on the carrier structure; a first insulating layer formed on the carrier structure; a first antenna structure coupled to the first insulating layer and electrically connected to the first electronic component; and a second antenna structure embedded in the carrier structure. As such, the electronic package provides more antenna functions within a limited space so as to improve the signal quality and transmission rate of electronic products. An electronic device having the electronic package is also provided. The electronic device is applicable to an electronic product having an antenna function.

A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective.

The present invention discloses a wireless package with a resilient connector for connecting a substrate to an antenna. The antenna is disposed directly on a top surface of a molding compound of the wireless package. The resilient connector has a lower terminal bonded to the substrate, a horizontal contact portion, and an oblique support portion integrally extending between the horizontal contact portion and the lower terminal. The horizontal contact portion has a flat top surface that is coplanar with the top surface of the molding compound and is in direct contact with the antenna such that the contact resistance distribution is concentrated and the production yield of the wireless package is improved.

The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The structure includes: a crackstop structure comprising dual rails surrounding an active area of an integrated circuit; and a through-BOx electrical contact electrically connecting each of the dual rails to an underlying substrate.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a radio frequency (RF) die having a lateral surface area and a plurality of contacts on a face, where the RF die is embedded in the package substrate with the plurality of contacts facing towards the second surface of the package substrate, and an RF front end between the RF die and the first surface of the package substrate, where the RF front end is positioned under the RF die and does not extend beyond the lateral surface area of the RF die.

A high-frequency module includes a circuit board including wiring patterns, a resin on an active element mounted on the circuit board and a side of the circuit board and sealing the active element, and connection conductors penetrating the resin from a surface of the resin and provided on a top surface of the active element. The active element includes a first connection electrode on a surface facing the circuit board, and a second connection electrode on a top surface opposite to the surface facing the circuit board. The first connection electrode is connected to a wiring pattern on the circuit board, and the second connection electrode is connected to the connection conductor and an outer electrode and is not connected to the wiring pattern.

Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).

In one example, a device having integrated package interference isolation includes a ground pad, an integrated circuit device die secured to the ground pad, a substrate secured to the ground pad, at least one a high-frequency, high-power semiconductor device secured to a top mounting surface of the substrate. For electromagnetic isolation, the integrated circuit device die includes a top metal, and the substrate includes a metal via electrically coupled to a metal trace that extends on the top mounting surface of the substrate. The device package also includes a number of ground pad bonding wires that electrically couple the redistribution layer of the integrated circuit device die and the metal trace to the ground pad. The redistribution layer of the integrated circuit device die and the metal trace and via of the substrate help to shield electromagnetic radiation between components in the device package.

In one example, a device having integrated package interference isolation includes a ground pad, an integrated circuit device die secured to the ground pad, a substrate secured to the ground pad, at least one a high-frequency, high-power semiconductor device secured to a top mounting surface of the substrate. For electromagnetic isolation, the integrated circuit device die includes a top metal, and the substrate includes a metal via electrically coupled to a metal trace that extends on the top mounting surface of the substrate. The device package also includes a number of ground pad bonding wires that electrically couple the redistribution layer of the integrated circuit device die and the metal trace to the ground pad. The redistribution layer of the integrated circuit device die and the metal trace and via of the substrate help to shield electromagnetic radiation between components in the device package.