Patent classifications
H01L2223/6683
MICROELECTRONIC DEVICE PACKAGE INCLUDING ANTENNA AND SEMICONDUCTOR DEVICE
A described example includes: an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.
Microwave integrated circuits including gallium-nitride devices on silicon
Various integrated circuits formed using gallium nitride and other materials are described. In one example, an integrated circuit includes a first integrated device formed over a first semiconductor structure in a first region of the integrated circuit, a second integrated device formed over a second semiconductor structure in a second region of the integrated circuit, and a passive component formed over a third region of the integrated circuit, between the first region and the second region. The third region comprises an insulating material, which can be glass in some cases. Further, the passive component can be formed over the glass in the third region. The integrated circuit is designed to avoid electromagnetic coupling between the passive component, during operation of the integrated circuit, and interfacial parasitic conductive layers existing in the first and second semiconductor structures, to improve performance.
PACKAGED INTEGRATED CIRCUIT DEVICE WITH BUILT-IN BALUNS
A packaged integrated circuit (IC) includes an IC die having first and second external contacts and a package substrate. The IC die is attached to the package substrate which includes a balun in a first metal layer. The balun is connected to the first and second external contacts of the IC die and to a first external contact of the package substrate. The first and second external contacts of the IC die communicate a differential signal with the package substrate, and the first external contact of the package substrate communicates a single-ended signal corresponding to the differential signal. Alternatively, the balun is connected to an external contact of the IC die and to first and second external contacts of the package substrate, in which the external contact of the IC die communicates a single-ended signal and the first and second external contacts of the package substrate communicate a differential signal.
Integrated circuit (IC) package with embedded heat spreader in a redistribution layer (RDL)
An integrated circuit (IC) package with an embedded heat spreader in a redistribution layer (RDL) is provided. IC packaging facilitates a high density package for ICs, including monolithic microwave integrated circuits (MMICs). However, IC packaging may result in reduced heat removal from an IC, decreasing radio frequency (RF) circuit performance. In an exemplary aspect, an IC package is provided which incorporates an embedded heat spreader within a dielectric layer of an RDL coupled to an IC die. The embedded heat spreader provides efficient heat transfer, robust RF performance, and operation through millimeter wave (mmW) frequencies, all in a miniature low-cost, low-profile surface mountable (SM) package.
Power Amplifier and Doherty Amplifier Comprising the Same
Example embodiments relate to power amplifiers and Doherty amplifiers that include the same. One example embodiment includes a power amplifier. The power amplifier includes one or more radiofrequency (RF) output terminals. The power amplifier also includes a Gallium Nitride (GaN) semiconductor die on which a power field-effect transistor (FET) is integrated. The FET includes a plurality of FET cells that are adjacently arranged in a row. The FET cells are connected either directly or indirectly to the one or more RF output terminals via a respective first inductor. For FET cells arranged at opposing ends of the row of FET cells, a total FET cell gate width and an inductance of the first inductor is larger and smaller than the total FET cell gate width and inductance of the first inductor for one or more FET cells arranged in the middle of the row of FET cells, respectively.
CHIP STRUCTURE AND WIRELESS COMMUNICATION APPARATUS
Example chip structures are described. One example chip structure includes a die, a first chip bond pad, and a second chip bond pad. A first radio frequency circuit, a second radio frequency circuit, a first interconnect metal wire, and a second interconnect metal wire are disposed in the die. The first interconnect metal wire is connected to the first radio frequency module, and is configured to provide an alternating current ground for the first radio frequency module. The second interconnect metal wire is connected to the second radio frequency module, and is configured to provide an alternating current ground for the second radio frequency module. The first chip bond pad and the second chip bond pad are disposed on a surface of the die.
ALUMINUM-BASED GALLIUM NITRIDE INTEGRATED CIRCUITS
Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.
MICROWAVE INTEGRATED CIRCUITS INCLUDING GALLIUM-NITRIDE DEVICES ON SILICON
Various methods of forming integrated circuits formed using gallium nitride and other materials are described. An example method includes forming a first integrated device over a first semiconductor structure in a first region of the integrated circuit, forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit, etching a cavity in a third region of the of the integrated circuit located between the first region and the second region, filling the cavity with an insulating material, and forming a passive component over the insulating material in the third region of the integrated circuit. In other aspects, the method can include grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure and, after the grinding, forming a ground plane over the back side of the semiconductor substrate.
INTEGRATED CIRCUIT (IC) PACKAGE WITH EMBEDDED HEAT SPREADER IN A REDISTRIBUTION LAYER (RDL)
An integrated circuit (IC) package with an embedded heat spreader in a redistribution layer (RDL) is provided. IC packaging facilitates a high density package for ICs, including monolithic microwave integrated circuits (MMICs). However, IC packaging may result in reduced heat removal from an IC, decreasing radio frequency (RF) circuit performance. In an exemplary aspect, an IC package is provided which incorporates an embedded heat spreader within a dielectric layer of an RDL coupled to an IC die. The embedded heat spreader provides efficient heat transfer, robust RF performance, and operation through millimeter wave (mmW) frequencies, all in a miniature low-cost, low-profile surface mountable (SM) package.
HIGH FREQUENCY SEMICONDUCTOR DEVICE AND PACKAGE THEREFOR
A high frequency semiconductor device package includes a metal plate, a frame body, a first lead part, a second lead part, a first conductive layer, and a second conductive layer. The frame body includes a first frame part made and a second frame part. The first frame part has a lower surface bonded to the metal plate. The first frame part has an upper surface including a first region and a second region. The first lead part protrudes outward along a line passing through a central part of the first region and a central part of the second region in plan view. The second lead part protrudes outward along the line in plan view. The first conductive layer includes a first stripe part and a first connection part. The second conductive layer includes a second stripe part and a second connection part.