Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die may not have circuitry for accessing the memory array. Further, the first and second dies may be bonded to function as a single memory device, and front surfaces of the first and second dies are conjoined to form electrical connections therebetween. The second die may include a portion uncovered by the first die, where bond pads of the semiconductor die stack are located. The first die may provide a space for bond wires to connect to the bond pads without interfering with another die attached above the semiconductor die stack. Multiple semiconductor die stacks may be stacked on top of and in line with each other.

Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die may not have circuitry for accessing the memory array. Further, the first and second dies may be bonded to function as a single memory device, and front surfaces of the first and second dies are conjoined to form electrical connections therebetween. The second die may include a portion uncovered by the first die, where bond pads of the semiconductor die stack are located. The first die may provide a space for bond wires to connect to the bond pads without interfering with another die attached above the semiconductor die stack. Multiple semiconductor die stacks may be stacked on top of and in line with each other.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.

Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.

A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.

A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.

A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.