Provided is an electric circuit body including: a power semiconductor element; a first conductor plate configured to be connected to one surface of the power semiconductor element; a first sheet-shaped member having a first resin insulation layer and configured to at least cover a surface of the first conductor plate; a sealing material configured to seal each of the power semiconductor element, the first conductor plate, and an end of the first sheet-shaped member; and a first cooling member configured to be adhesively attached to the first sheet-shaped member. In the electric circuit body, the first sheet-shaped member includes : an embedded portion where the end of the first sheet-shaped member is covered with the sealing material; a heat dissipation surface as a region to overlap the surface of the first conductor plate; and a margin as a region between the embedded portion and the heat dissipation surface, the margin is located more inward than the heat dissipation surface, and the embedded portion is located more inward than the margin.

A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.

A semiconductor module includes: a first switch element; a second switch element; a first conductor that is joined to the source electrode of the first switch element, the first switch element is placed on the first conductor; a second conductor that is joined to the source electrode of the second switch element, the second switch element is placed on the second conductor; a positive electrode conductor connected to the drain electrode of the first switch element; an output conductor connected to the first conductor and the drain electrode of the second switch element; a negative electrode conductor connected to the second conductor; a first control conductor connected to the gate electrode of the first switch element; a second control conductor connected to the gate electrode of the second switch element; a first voltage detection terminal provided on the first conductor; a second voltage detection terminal provided on the second conductor; and an exterior resin part having a polyhedral shape. The first voltage detection terminal and the second voltage detection terminal protrude from different exterior surfaces of the exterior resin part.

A semiconductor chip stack module that includes a substrate, two first semiconductor chips supported by the substrate, and a second semiconductor chip stacked on both of the two first semiconductor chips. The second semiconductor chip is electrically connected to both of the two first semiconductor chips by a conductive paste configured between the second semiconductor chip and both of the two first semiconductor chips. As multiple standard chips are stacked in the power module, and their number as well as the connection methods (e.g. series or parallel) are flexible so that the user can choose which electric characteristic(s) to be increased in the power module with the stacked chips.

A performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip, and a clip mounted on the semiconductor chip via a silver paste. Here, the semiconductor chip includes a passivation film having an opening, a source pad of a main transistor having a portion exposed from the passivation film at the opening, and a wall portion provided on the passivation film so as to surround the source pad in a plan view. At this time, a whole of the portion (exposed surface) of the source pad, which is exposed from the passivation film, is covered with the silver paste. Further, in the plan view, the silver paste connecting the source pad with the clip is positioned inside of an area surrounded by the wall portion, without overflowing.

A semiconductor die and an electrically conductive ribbon are arranged on a substrate. The electrically conductive ribbon includes a roughened surface. An insulating encapsulation is molded onto the semiconductor die and the electrically conductive ribbon. The roughened surface of the electrically conductive ribbon provides a roughened coupling interface to the insulating encapsulation.

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.