Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

A package has a first region and a second region. The package includes a first die, a second die, an encapsulant, and an inductor. The second die is stacked on and bonded to the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. A metal density in the first region is greater than a metal density in the second region.

A bonded structure is disclosed. The bonded structure can include an interconnect structure that has a first side and a second side opposite the first side. The bonded structure can also include a first die that is mounted to the first side of the interconnect structure. The first die can be directly bonded to the interconnect structure without an intervening adhesive. The bonded structure can also include a second die that is mounted to the first side of the interconnect structure. The bonded structure can further include an element that is mounted to the second side of the interconnect structure. The first die and the second die are electrically connected by way of at least the interconnect structure and the element.

Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

A light-emitting diode (LED) array is formed by bonding an LED chip or wafer to a backplane substrate via curved interconnects. The backplane substrate may include circuits for driving the LED's. One or more curved interconnects are formed on the backplane substrate. A curved interconnect may be electrically connected to a corresponding circuit of the backplane substrate, and may include at least a portion with curvature. The LED chip or wafer may include one or more LED devices. Each LED device may have one or more electrical contacts. The LED chip or wafer is positioned above the backplane substrate to spatially align electrical contacts of the LED devices with the curved interconnects on the backplane substrate. The electrical contacts are bonded to the curved interconnects to electrically connect the LED devices to corresponding circuits of the backplane substrate.

A parameter adjustment method includes an acquisition process and a parameter changing process. The acquisition process acquires, from an inspection apparatus configured to inspect a combined substrate in which the first substrate and the second substrate are bonded by the bonding apparatus, an inspection result indicating a direction and a degree of distortion occurring in the combined substrate. The parameter changing process changes at least one of multiple parameters including at least one of the gap, an attraction pressure of the first substrate by the first holder, an attraction pressure of the second substrate by the second holder or a pressing force on the first substrate by the striker, based on trend information indicating a tendency of a change in the direction and the degree of the distortion when each of the multiple parameters is changed and the inspection result acquired in the acquiring of the inspection result.

A parameter adjustment method includes an acquisition process and a parameter changing process. The acquisition process acquires, from an inspection apparatus configured to inspect a combined substrate in which the first substrate and the second substrate are bonded by the bonding apparatus, an inspection result indicating a direction and a degree of distortion occurring in the combined substrate. The parameter changing process changes at least one of multiple parameters including at least one of the gap, an attraction pressure of the first substrate by the first holder, an attraction pressure of the second substrate by the second holder or a pressing force on the first substrate by the striker, based on trend information indicating a tendency of a change in the direction and the degree of the distortion when each of the multiple parameters is changed and the inspection result acquired in the acquiring of the inspection result.

A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first tier includes forming a conductive via extending from a lower portion of a first interconnect structure into a first semiconductor substrate underlying the lower portion; forming an upper portion of the first interconnect structure on the conductive via and the lower portion; forming a first surface dielectric layer on the upper portion; and forming a first and a second bonding connectors in the first surface dielectric layer. The first bonding connector extends to be in contact with an upper-level interconnecting layer of the first interconnect structure, the second bonding connector is narrower than the first bonding connector and extends to be in contact with a lower-level interconnecting layer of the first interconnect structure, and a top surface of the conductive via is between the upper-level interconnecting layer and the first semiconductor substrate.