Semiconductor packages are provided. The semiconductor package includes a first semiconductor chip to which a first elevated pillar bump is connected, a second semiconductor chip stacked on the first semiconductor chip to leave revealed the first elevated pillar bump and configured to include a first chip pad disposed on a center region of the second semiconductor chip, a third semiconductor chip offset and stacked on the second semiconductor chip to leave revealed the first chip pad, and a chip supporter supporting an overhang of the third semiconductor chip.

A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

A method includes placing a first plurality of dies over a carrier. The first plurality of dies include at least a first logic die and a first memory die, placing a second plurality of dies over the first plurality of dies. The second plurality of dies are electrically coupled to the first plurality of dies, and include at least a second logic die and a second memory die. A third plurality of dies are placed over the second plurality of dies, and are electrically coupled to the first plurality of dies and the second plurality of dies. The third plurality of dies include at least a third logic die and a third memory die. The method further includes forming electrical connectors over and electrically coupling to the first plurality of dies, the second plurality of dies, and the third plurality of dies.

A method includes placing a first plurality of dies over a carrier. The first plurality of dies include at least a first logic die and a first memory die, placing a second plurality of dies over the first plurality of dies. The second plurality of dies are electrically coupled to the first plurality of dies, and include at least a second logic die and a second memory die. A third plurality of dies are placed over the second plurality of dies, and are electrically coupled to the first plurality of dies and the second plurality of dies. The third plurality of dies include at least a third logic die and a third memory die. The method further includes forming electrical connectors over and electrically coupling to the first plurality of dies, the second plurality of dies, and the third plurality of dies.

A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.

A fan-out semiconductor package includes a first connection member having a through-hole, first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating at least portions of the first connection member, the first semiconductor chip, and the second semiconductor chip, and a second connection member disposed on the first connection member and on active surfaces of the first semiconductor chip and the second semiconductor chip. A redistribution layer of the second connection member is respectively connected to both the first and second connection pads through first and second conductors, and the second conductor has a height greater than that of the first conductor.

In a general aspect, a package includes an optical sensor die fabricated in a semiconductor wafer. The optical sensor die has an optically active area on a front side of the semiconductor wafer generating a raw image signal. A transparent cover attached to the front side of the semiconductor wafer above the optically active area of the optical sensor die. An image signal processor (ISP) die processing the raw image signal is embedded in a layer of molding material attached to a back side the semiconductor wafer opposite the front side of the semiconductor wafer.