A sheet for sintering bonding 10 of the present invention comprises an electrically conductive metal containing sinterable particle and a binder component, and upon subjecting the sheet to a pressurization treatment onto a silver plane of a 5 mm square Si chip under predetermined conditions, the ratio of the area of a layer of a material for sintering bonding transferred onto the silver plane to the silver plane area is 0.75 to 1. A sheet body X of the present invention has a laminated structure comprising a base material B and the sheet 10. A semiconductor chip with a layer of a material for sintering bonding of the present invention comprises a semiconductor chip and a material layer derived from the sheet 10 on one face of the chip, and the ratio of the area of the material layer to the area of that face is 0.75 to 1.

The present invention provides a film-shaped firing material 1 including sinterable metal particles 10, and a binder component 20, in which a content of the sinterable metal particles 10 is in a range of 15% to 98% by mass, a content of the binder component 20 is in a range of 2% to 50% by mass, a tensile elasticity of the film-shaped firing material at 60 C. is in a range of 4.0 to 10.0 MPa, and a breaking elongation thereof at 60 C. is 500% or greater; and a film-shaped firing material with a support sheet including the film-shaped firing material 1 which contains sinterable metal particles and a binder component, and a support sheet 2 which is provided on at least one side of the film-shaped firing material, in which an adhesive force (a2) of the film-shaped firing material to the support sheet is smaller than an adhesive force (a1) of the film-shaped firing material to a semiconductor wafer, the adhesive force (a1) is 0.1 N/25 mm or greater, and the adhesive force (a2) is in a range of 0.1 N/25 mm to 0.5 N/25 mm.

A wafer-level packaging method includes providing a base substrate and providing first chips. A photolithographic bonding layer is formed on the base substrate or on the first chips. First vias are formed in the photolithographic bonding layer. The first chips are pre-bonded to the base substrate through a photolithographic bonding layer with each first chip corresponding to a first via. A thermal compression bonding process is used to bond the first chips to the base substrate such that an encapsulation material fills between adjacent first chips and covers the first chips and the base substrate. The base substrate is etched to form second vias through the base substrate with each second via connected to a first via to form a first conductive via. A first conductive plug is formed in the first conductive via to electrically connect to a corresponding first chip.

This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding material. The semiconductor element comprises: a base; a first conductive layer that is provided on a first surface of the base, said first surface being on the substrate side; and a second conductive layer that is provided on a second surface of the base, said second surface being on the reverse side of the first surface. The thickness of the first conductive layer is from 0.5 times to 2.0 times (inclusive) the thickness of the second conductive layer.

A mounting apparatus for stacking and mounting two or more semiconductor chips at a plurality of locations on a substrate includes: a first mounting head for forming, at a plurality of locations on the substrate, temporarily stacked bodies in which two or more semiconductor chips are stacked in a temporarily press-attached state; and a second mounting head for forming chip stacked bodies by sequentially finally press-attaching the temporarily stacked bodies formed at the plurality of locations. The second mounting head includes: a press-attaching tool for heating and pressing an upper surface of a target temporarily stacked body to thereby finally press-attach the two or more semiconductor chips configuring the temporarily stacked body altogether; and one or more heat-dissipation tools having a heat-dissipating body which, by coming into contact with an upper surface of another stacked body positioned around the target temporarily stacked body, dissipates heat from the another stacked body.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

This disclosure is related to post processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices. In another example, color conversion layers are integrated into the system substrate to create different output from the micro devices.

A method of liquid assisted micro cold binding is provided. The method includes: forming a conductive pad on the substrate in which the conductive pad consists essentially of indium; forming a liquid layer on the conductive pad; placing a micro device having an electrode facing the conductive pad over the conductive pad such that the micro device is in contact with the liquid layer and is gripped by a capillary force produced by the liquid layer between the micro device and the conductive pad in which the electrode consists essentially of indium; and evaporating the liquid layer such that the electrode is bound to the conductive pad and is in electrical contact with the conductive pad.

A wafer-level packaging method using a photolithographic bonding material includes providing a base substrate; providing a plurality of first chips; forming a photolithographic bonding layer on the base substrate or on the first chips; forming a plurality of first vias in the photolithographic bonding layer; pre-bonding the first chips to the base substrate through the photolithographic bonding layer with each first chip corresponding to a first via; using a thermal compression bonding process to bond the first chips to the base substrate such that an encapsulation material fills between adjacent first chips and covers the first chips and the base substrate; etching the base substrate to form a plurality of second vias through the base substrate with each second via connected to a first via to form a first conductive via; and forming a first conductive plug in the first conductive via to electrically connect to a corresponding first chip.