This application is directed to a stacked semiconductor device assembly including first and second integrated circuit (IC) devices. Each of the first and second IC devices further includes a master interface, a channel master circuit configured to receive read/write data using the master interface, a slave interface, a channel slave circuit configured to receive read/write data using the slave interface, a memory core coupled to the channel salve circuit, and a modal pad. The first and second IC devices are configured such that in response to at least a modal selection signal received at one of the modal pads of the first and second IC devices, one of the first and second IC devices is configured to receive read/write data using its respective charnel master circuit, and the other of the first and second IC devices is configured to receive read/write data using its respective channel slave circuit.

In an embodiment, a device includes: a plurality of redistribution lines over a semiconductor substrate, the redistribution lines including trace portions extending along the semiconductor substrate; a first passivation layer over the redistribution lines, the first passivation layer filling an entirety of an area between the trace portions of the redistribution lines; a passive device over the first passivation layer; a dielectric layer over the passive device; and a die connector extending through the dielectric layer, the die connector physically and electrically coupled to the passive device.

A semiconductor package includes: a plurality of first semiconductor chips; a second semiconductor chip including a front surface and disposed on the plurality of first semiconductor chips, and wherein the second semiconductor chip further includes a first dummy pad located on a back surface thereof; and a third semiconductor chip including a front surface and disposed on the second semiconductor chip. The third semiconductor chip further includes a second dummy pad located on the front surface thereof. The first dummy pad is disposed on at least a part of a back surface edge region that is adjacent to a side surface of the second semiconductor chip. The second dummy pad is disposed on at least a part of a front surface edge region that is adjacent to a side surface of the third semiconductor chip. The first dummy pad and the second dummy pad are bonded to each other.

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

A method for fault isolation includes: acquiring a thermal imaging picture of a surface of a to-be-tested chip, the thermal imaging picture being obtained by scanning the to-be-tested chip to which a test signal is applied through an infrared thermal imaging device, and analyzing the thermal imaging picture to obtain a phase angle of each point on the surface of the to-be-tested chip; acquiring a three-dimensional image of the surface of the to-be-tested chip, the three-dimensional image being obtained by scanning the to-be-tested chip to which the test signal is applied through an image scanning device, and analyzing the three-dimensional image to obtain a three-dimensional coordinate of each point on the surface of the to-be-tested chip; calculating a three-dimensional coordinate of the fault in the to-be-tested chip according to the phase angle and the three-dimensional coordinate of each point on the surface of the to-be-tested chip.

A manufacturing method of a semiconductor device includes: a first step of, after joining a wire to an electrode using a capillary, forming a wire part by moving the capillary to a third target point while feeding out the wire; a second step of forming a bent part by moving the capillary to a fourth target point while feeding out the wire; a third step of processing the bent part into a planned cut part by repeating lowering and raising of the capillary for multiple times; and a fourth step of cutting the wire at the planned cut part by raising the capillary with a wire clamper closed to form a pin wire.

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies.

A three-dimensional (3D) stacked chip is described. The 3D stacked chip includes a first die having a front-side surface and a backside surface, opposite the front-side surface. The backside surface on a front-side surface of a first redistribution layer (RDL). The 3D stacked chip also includes a second die having a front-side surface on the front-side surface of the first die and a backside surface being distal from the first RDL. The 3D stacked chip further includes a via extending from the backside surface of the second die to a back-end-of-line (BEOL) layer of the second die.

In an embodiment, a device includes: a plurality of redistribution lines over a semiconductor substrate, the redistribution lines including trace portions extending along the semiconductor substrate; a first passivation layer over the redistribution lines, the first passivation layer filling an entirety of an area between the trace portions of the redistribution lines; a passive device over the first passivation layer; a dielectric layer over the passive device; and a die connector extending through the dielectric layer, the die connector physically and electrically coupled to the passive device.