An electronic structure includes a packaging structure, a circuit pattern structure, an underfill and a protrusion structure. The circuit pattern structure is disposed over the packaging structure. A gap is between the circuit pattern structure and the packaging structure. The underfill is disposed in the gap. The protrusion structure is disposed in the gap, and is configured to facilitate the distributing of the underfill in the gap.

A semiconductor device includes a first chip package, a heat dissipation structure and an adapter. The first chip package includes a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die has an active surface and a back surface opposite to the active surface. The heat dissipation structure is connected to the chip package. The adapter is disposed over the first chip package and electrically connected to the semiconductor die.

A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.

Provided is a semiconductor module including: a multilayer insulating substrate comprising at least two metal layers which are insulated from each other and an insertion groove to which at least one first semiconductor component is inserted, wherein one surface or the other surface of the at least one first semiconductor component is electrically connected to the metal layers by using a bonding layer interposed therebetween; an insulating material which surrounds at least two surfaces of the first semiconductor component in the insertion groove; radiation substrates which are electrically or structurally bonded to one surface or the other surface of the at least one first semiconductor component; and at least one second semiconductor component which is installed on an upper surface, a lower surface, or both upper and lower surfaces of the multilayer insulating substrate, wherein a depth of the insertion groove is greater than a depth of the first semiconductor component. Accordingly, high power may be controlled and heat generated by high power may be radiated.

A semiconductor package is provided. The semiconductor package includes: a first redistribution substrate; a semiconductor chip provided on the first redistribution substrate; a molding layer provided on the first redistribution substrate and the semiconductor chip; and a second redistribution substrate provided on the molding layer. The second redistribution substrate includes: redistribution patterns spaced apart from one another; a first dummy conductive pattern spaced apart from the redistribution patterns; an insulating layer provided on the first dummy conductive pattern; and a marking metal layer provided on the insulating layer and spaced apart from the first dummy conductive pattern. Sidewalls of the marking metal layer overlap the first dummy conductive pattern along a vertical direction perpendicular to an upper surface of the first redistribution substrate.

A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.

In a manufacturing method for a packaging structure, a flexible substrate is provided, wherein the flexible substrate includes a hard plate region, a winding region and a fan-out region, a first wiring layer is formed on one side of the flexible substrate, multiple flexible substrates are laminated and bonded in a hard plate region to form a multi-layer stack structure, in a hard plate region of the multi-layer stack structure, a copper pillar is manufactured for interlayer connection, a second wiring layer connected to the copper pillar is manufactured on two sides of the hard plate region, a dielectric material of the multi-layer stack structure is removed on two sides of the winding region and the fan-out region, and a chip is packaged, and after some or all of the fan-out regions are bent through the winding region, the fan-out regions are stacked with the hard plate region.