The foldable display panel includes a substrate and a pixel array. The substrate has a surface and display and periphery areas thereon. The periphery area is on at least one side of the display area, and has first and second bonding areas. The first and second bonding areas are at opposite first and second sides of the periphery area, respectively. The first and second bonding areas are spaced apart by a first distance along a first direction. The substrate has a foldable line passing through a center of the display area between the first and the second bonding areas. The first and second sides are on two sides of the foldable line. The pixel array is on the display area and overlaps the foldable line. The pixel array is between the first and second sides and includes sub pixel units arranged in an array.

A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.

A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.

Analyte sensor connectors that connect analyte sensors, e.g., conductive members of analyte sensors, to other devices such as sensor electronics units, e.g., sensor control units, are provided. Also provided are systems that include analyte sensors, analyte sensor connectors, and analyte sensor electronics units, as well as methods of establishing and maintaining connections between analyte sensors and analyte sensor electronics units, and methods of analyte monitoring/detection. Also provided are methods of making analyte sensor connectors and systems that include analyte sensor connectors.

Analyte sensor connectors that connect analyte sensors, e.g., conductive members of analyte sensors, to other devices such as sensor electronics units, e.g., sensor control units, are provided. Also provided are systems that include analyte sensors, analyte sensor connectors, and analyte sensor electronics units, as well as methods of establishing and maintaining connections between analyte sensors and analyte sensor electronics units, and methods of analyte monitoring/detection. Also provided are methods of making analyte sensor connectors and systems that include analyte sensor connectors.

An adsorption device includes a magnetic plate and a limiting layer. A surface of the magnetic plate includes a first region and a plurality of second regions spaced apart from each other. The first region and each second region do not overlap with each other. The first region forms a magnetic pole of the magnetic plate, and each second region forms the opposite magnetic pole of the magnetic plate. The limiting layer covers the first region. Each second region is exposed to the limiting layer and configured for adsorbing a small-scale LED as a target object.

A semiconductor package having an aperture in a die pad and solder in the aperture coplanar with a surface of the package is disclosed. The package includes a die pad, a plurality of leads, and a semiconductor die coupled to the die pad with a die attach material. A cavity or aperture is formed through the die pad to expose a portion of the die attach material. Multiple solder reflows are performed to reduce the presence of voids in the die attach material. In a first solder reflow, the voids of trapped gas that form when attaching the die to the die pad are released. Then, in a second solder reflow, solder is added to the aperture coplanar with a surface of the die pad. The additional solder can be the same material as the die attach material or a different material.

A semiconductor package having an aperture in a die pad and solder in the aperture coplanar with a surface of the package is disclosed. The package includes a die pad, a plurality of leads, and a semiconductor die coupled to the die pad with a die attach material. A cavity or aperture is formed through the die pad to expose a portion of the die attach material. Multiple solder reflows are performed to reduce the presence of voids in the die attach material. In a first solder reflow, the voids of trapped gas that form when attaching the die to the die pad are released. Then, in a second solder reflow, solder is added to the aperture coplanar with a surface of the die pad. The additional solder can be the same material as the die attach material or a different material.

Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.

Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.