There is provided a semiconductor module capable of determining a semiconductor chip in which a short-circuit failure has occurred without being disassembled. A semiconductor module includes IGBT provided in each of semiconductor chips connected in parallel, switching of which being controlled by a gate voltage based on a gate signal; two external terminals input with the gate signal; a first connection route group having a first connection route and a third connection route connecting the external terminal and the IGBTs provided in the semiconductor chips respectively; and a second connection route group having a second connection route and a fourth connection route connecting the external terminal and the IGBTs provided in the semiconductor chips respectively.

A semiconductor device includes a semiconductor chip, a substrate having a main surface on which the semiconductor chip is arranged, a resin case which has a storage space therein and a side wall, the side wall having an injection path extending from the storage space to a device exterior, the resin case having a first opening at a bottom side thereof, connecting the storage space to the device exterior, the substrate being disposed on the resin case, at a main surface side of the substrate facing at the bottom side of the resin case, and a sealing material filling the storage space and the injection path.

A relay substrate in which a circuit pattern and an external electrode are integrated on a insulating plate is used in the semiconductor device. Such configuration makes it possible to reduce a resistance in a current path while preventing the problems occurring when the external electrode is soldered on the semiconductor chip.

A relay substrate in which a circuit pattern and an external electrode are integrated on a insulating plate is used in the semiconductor device. Such configuration makes it possible to reduce a resistance in a current path while preventing the problems occurring when the external electrode is soldered on the semiconductor chip.

An electronic device includes electronic components and an epoxy resin portion which seals the electronic components. The electronic device is disposed in a refrigerant which cools the electronic components. A first layer having a three-dimensional crosslinking structure is formed on a surface or inside of the epoxy resin portion. The first layer is formed such that a length calculated by cube root of an average free volume in the three-dimensional crosslinking structure of the first layer is shorter than a length of the longest side of molecules forming the refrigerant.

The present disclosure relates to a power semiconductor module of which heat is dissipated by its both sides and provides a power semiconductor module technology in which a mold is formed in a surrounding space of a power semiconductor die, and then, wires are formed on upper and lower sides of the power semiconductor die and substrates are disposed on upper and lower sides of the wires.

A semiconductor power module in which a three-phase AC inverter is incorporated in a package includes first to third circuit patterns on which second, fourth, and sixth switching elements are mounted, respectively, and a fourth circuit pattern on which first, third, and fifth switching elements are mounted; a second main electrode to which all of main electrode wirings of the second, fourth, and sixth switching elements are connected; a second main electrode terminal connected to the second main electrode; a first main electrode electrically connected to the fourth circuit pattern; and a first main electrode terminal connected to the first main electrode, and each of the main electrode wirings of the second, fourth, and sixth switching elements is provided so that a main electrode wiring closer to the second main electrode terminal in a horizontal direction in plan view has a longer length.

A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.

Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.

A semiconductor device includes a normally-on junction FET having a gate electrode, a source electrode and a drain electrode and a normally-off MOSFET having a gate electrode, a source electrode and a drain electrode. The source electrode of the junction FET is electrically connected to the drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series. The gate electrode of the junction FET is electrically connected to the gate electrode of the MOSFET.