A semiconductor module includes a conductor layer, an insulating plate, a circuit pattern layer, and semiconductor chips disposed in this order. The conductor layer has a first through hole. The insulating plate has a second through hole having an opening size larger than the first through hole at a location facing the first through hole. The circuit pattern layer has an opening having an opening size larger than the second through hole at a location facing the second through hole. When the semiconductor module is connected to a cooling member, heat transfer medium is disposed between the conductor layer and the cooling member. A screw member is inserted into the opening and second and first through holes and screwed into a screw attachment hole. The screw member presses an area around the first through hole inside the second through hole toward the cooling member.

A semiconductor device includes: an insulating sheet including a first main surface and a second main surface; a first terminal in a shape of a plate provided to face the first main surface of the insulating sheet and including a first protruding portion protruding outward from the first main surface of the insulating sheet; and a second terminal in a shape of a plate provided to face the second main surface of the insulating sheet and including a second protruding portion protruding outward from the second main surface of the insulating sheet side by side with the first protruding portion, wherein a first recessed portion is provided at a position of the first protruding portion intersecting an end portion of the insulating sheet by concaving a side surface of the first protruding portion facing the second protruding portion in a direction away from the second protruding portion.

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

A half bridge GaN circuit is disclosed. The circuit includes a low side circuit, which has a low side switch, a low side switch driver configured to drive the low side switch, a first level shift circuit configured to receive a first level shift signal, and a second level shift circuit configured to generate a second level shift signal. The half bridge GaN circuit also includes a high side circuit, which has a high side switch configured to be selectively conductive according to a voltage level of a received high side switch signal, and a high side switch driver configured to generate the high side switch signal in response to the level shift signals. A transition in the voltage of the high side switch signal causes the high side switch driver to prevent additional transitions of the voltage level of the high side switch signal for a period of time.

A half bridge GaN circuit is disclosed. The circuit includes a low side circuit, which has a low side switch, a low side switch driver configured to drive the low side switch, a first level shift circuit configured to receive a first level shift signal, and a second level shift circuit configured to generate a second level shift signal. The half bridge GaN circuit also includes a high side circuit, which has a high side switch configured to be selectively conductive according to a voltage level of a received high side switch signal, and a high side switch driver configured to generate the high side switch signal in response to the level shift signals. A transition in the voltage of the high side switch signal causes the high side switch driver to prevent additional transitions of the voltage level of the high side switch signal for a period of time.

A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.

A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.

An object of the invention is to manufacture a semiconductor module small. A metal wire (212) connecting a control electrode (101) and a control terminal (21) rises to form a first angle (θ1) from the control electrode (101) toward a first conductive portion (202), gradually goes in substantially parallel to the first conductive portion (202) as the metal wire approaches the first conductive portion (202), and is connected to the control terminal (21) to form a second angle (θ2) smaller than the first angle (θ1).

An insulated circuit board includes an insulated substrate, a first electrode, and a second electrode. A thin portion is formed in a corner portion, the corner portion being a region occupying, with regard to directions along outer edges from a vertex of at least one of the first and second electrodes in plan view, a portion of a length of the outer edges, and the thin portion has a thickness smaller than that of a region other than the thin portion. The thin portion in at least one of the first and second electrodes has a planar shape surrounded by first and second sides orthogonal to each other as portions of the outer edges from the vertex, and a curved portion away from the vertex of the first and second sides.