Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.

Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.

An object of the present invention is to provide an electrically conductive paste and a sintered body thereof having a low electric resistance value and excellent electrical conductivity when made into a sintered body.

An electrically conductive paste comprising: a flake-like silver powder having a median diameter D50 of 15 μm or less; a silver powder having a median diameter D50 of 25 μm or more; and a solvent, wherein the content of the flake-like silver powder is 15 to 70 parts by mass and the content of the silver powder having a median diameter D50 of 25 μm or more is 30 to 85 parts by mass based on 100 parts by mass in total of the flake-like silver powder and the silver powder having a median diameter D50 of 25 μm or more.

According to one configuration, an inductor device comprises: core material and one or more electrically conductive paths. The core material is magnetically permeable and surrounds (envelops) the one or more electrically conductive paths. Each of the electrically conductive paths extends through the core material of the inductor device from a first end of the inductor device to a second end of the inductor device. The magnetically permeable core material is operative to confine (guide, carry, convey, localize, etc.) respective magnetic flux generated from current flowing through a respective electrically conductive path. The core material stores the magnetic flux energy (i.e., first magnetic flux) generated from the current flowing through the first electrically conductive path. One configuration herein includes a power converter assembly comprising a stack of components including the inductor device as previously described as well as a first power interface, a second power interface, and one or more switches.

An object of the present disclosure is to provide a semiconductor device capable of confirming withstand voltage of a snubber circuit after providing the snubber circuit and a method of manufacturing the semiconductor device. A semiconductor device according to the present disclosure includes: an insulating substrate; a circuit patterns provided on the insulating substrate; a snubber circuit substrate provided on the insulating substrate separately from the circuit patterns; a resistance provided on one of the circuit patterns and the snubber circuit substrate; a capacitor provided on another one of the circuit patterns and the snubber circuit substrate; and at least one semiconductor element electrically connected to the resistance and the capacitor.

The present disclosure relates to a package structure. The package structure includes a semiconductor device, a first molding compound, a through-via, first and second dielectric layers, and a second molding compound in contact with a sidewall of the first dielectric layer. The first molding compound is in contact with a sidewall of the semiconductor device. The through-via is formed in the first molding compound and electrically connected to the semiconductor device. The first and second dielectric layers are formed at upper and lower sides of the semiconductor device. The at least one redistribution line is formed in the first dielectric layer and electrically connected to the semiconductor device and the through-via. The second molding compound is in contact with a sidewall of the first dielectric layer. The at least one redistribution line comprises an ESD-protection feature or a MIM (metal-insulator-metal) feature.

A semiconductor package includes a frame having a through-hole, and a first semiconductor chip disposed in the through-hole of the frame and having an active surface on which a connection pad is disposed, an inactive surface opposing the active surface, and a side surface connecting the active and inactive surfaces. A first encapsulant covers at least a portion of each of the inactive surface and the side surface of the first semiconductor chip. A connection structure has a first surface having disposed thereon the active surface of the first semiconductor chip, and includes a redistribution layer electrically connected to the connection pad of the first semiconductor chip. A first passive component is disposed on a second surface of the connection structure opposing the first surface, the first passive component being electrically connected to the redistribution layer and having a thickness greater than a thickness of the first semiconductor chip.

A semiconductor device includes a first electrode disposed on a substrate. A capacitor dielectric layer is on the first electrode. A second electrode is on the capacitor dielectric layer. A first insulating layer is on the first and second electrodes and the capacitor dielectric layer. A first interconnection structure is on the first insulating layer and connected to the first electrode. A second interconnection structure is on the first insulating layer and connected to the second electrode. A second insulating layer is on the first and second interconnection structures. A plurality of connection structures are configured to pass through the second insulating layer and be connected to the first and second interconnection structures. Each of the first and second interconnection structures has an aluminum layer.

A semiconductor device comprises two memory chips, one control chip controlling each memory chip, a signal transmission path through which a signal transmission between the control chip and each memory chip is performed, and a capacitance coupled onto the signal transmission path. Also, the capacitance (capacitor element) is larger than each parasitic capacitance parasitic on each chip. Accordingly, it is possible to perform the signal transmission of the semiconductor device at high speed.

A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.