A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the semiconductor substrate. The transistor amplifies an input signal supplied to an input end and outputs an amplified signal through an output end. The first harmonic termination circuit attenuates a harmonic component included in the amplified signal. The first harmonic termination circuit is formed at the semiconductor substrate such that one end of the first harmonic termination circuit is connected to the output end of the transistor and the other end of the first harmonic termination circuit is connected to a ground end of the transistor.

A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.

A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.

An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

The present disclosure relates to a semiconductor package that may include a package substrate with a first surface and an opposing second surface, a first device coupled to the first surface of the package substrate, a redistribution frame coupled to the second surface of the package substrate, a plurality of solder balls coupled to the second surface of the package substrate, a second device coupled to the redistribution frame, and a printed circuit board coupled to the plurality of solder balls on the second surface of substrate, wherein the redistribution frame coupled with the second device and the plurality of solder balls are positioned between the package substrate and the printed circuit board.

Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.

An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via.

A power module includes a power wiring line provided with a power element, a glass ceramic multilayer substrate provided with a control element to control the power element, and a highly heat-conductive ceramic substrate made of a ceramic material having higher thermal conductivity than a glass ceramic contained in the glass ceramic multilayer substrate. The power wiring line is disposed on the highly heat-conductive ceramic substrate, and the glass ceramic multilayer substrate is disposed directly on the highly heat-conductive ceramic substrate.

A composite ceramic multilayer substrate includes a glass ceramic insulating layer including a wiring layer and a highly thermally conductive ceramic insulating layer made of a ceramic material having a higher thermal conductivity than the glass ceramic insulating layer. The glass ceramic insulating layer is provided on at least one main surface of the highly thermally conductive ceramic insulating layer directly and/or with a wiring layer interposed therebetween. When viewed in a direction perpendicular or substantially perpendicular to a main surface of the composite ceramic multilayer substrate, the composite ceramic multilayer substrate includes at least one heat generating element-mounting portion surrounded by the glass ceramic insulating layer and at which a heat generating element-mounting wiring line provide on the main surface of the highly thermally conductive ceramic insulating layer is exposed.

Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system.