Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

An electric component comprising a terminal electrode and a hot-melt polymer layer formed on the terminal electrode, wherein the hot-melt polymer layer comprises (i) 100 parts by weight of a metal powder and (ii) 1 to 30 parts by weight of a polymer, wherein melt mass-flow rate (MFR) of the polymer is 0.5 to 20 g/10 min. at 120 to 200 C. and 0.3 to 8 kgf.

Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.

Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.

A disclosed circuit arrangement includes a flexible substrate. A layer of pressure sensitive adhesive (PSA) is directly adhered to a first major surface of the substrate. One or more metal foil pads and electrically conductive wire are attached directly on a surface of the PSA layer. The wire has a round cross-section and one or more portions directly connected to the one or more metal foil pads with one or more weld joints, respectively. An electronic device is attached directly on the surface of the layer of PSA and is electrically connected to the one or more portions of the round wire by one or more bond wires, respectively.

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

A LED chip has integrated capacitor and inductor structures, wherein a capacitor structure is coupled to an active LED structure of the LED chip, the inductor structure is coupled to the capacitor structure, and the inductor structure is configured to harvest power from an externally supplied radio frequency (RF) signal. At least portions of the inductor and capacitor are arranged in or on ceramic passivation material. A LED chip may have a footprint of no greater than 2.5 mm?2.5 mm, and/or a top area of no greater than 6.25 mm.sup.2. A resistor element or memristor element may be coupled between the capacitor structure and the active region. Methods of fabricating such LED chips are also provided.