Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

A semiconductor package device includes a substrate, a passive component, an active component and a package body. The passive component is disposed on the substrate. The active component is disposed on the substrate. The package body is disposed on the substrate. The package body includes a first portion covering the active component and the passive component, and a second portion covering the passive component. A top surface of the second portion of the package body is higher than a top surface of the first portion of the package body.

A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (first wires) extend from a surface of the substrate. Second wire bond wires (second wires) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

Various embodiments disclosed relate to a semiconductor package. The semiconductor package includes a substrate having first and second opposed major surfaces. The substrate further includes a cavity having a first end defined by a portion of the first major surface and a second end defined by a portion of the second major surface. The semiconductor package further includes a first electronic component attached to the first major surface. The first electronic component substantially covers the first end of the cavity. A second electronic component is at least partially disposed within the cavity.

The present disclosure attempts to improve performance of a semiconductor apparatus including a power transistor such as an IGBT. In a semiconductor apparatus, an IGBT module 110 includes IGBT elements SWa and SWb connected in parallel to each other, a resistor R1a connected to a gate terminal of the IGBT element SWa, and a diode D1a connected in parallel to the resistor R1a. In the diode D1a, a direction toward the gate terminal of the IGBT element SWa is a forward direction. With this configuration, it is possible to prevent gate oscillation and to improve switching characteristics.

A light emitting device includes a light emitting element; a sub-mount including a sub-mount substrate with a front surface on which the light emitting element is disposed, and a back surface electrode disposed in a back surface that is on a back side of the front surface of the sub-mount substrate; a main-mount in which the sub-mount is disposed, the main-mount including a front surface metal pattern including a wiring electrode bonded to the back surface electrode via solder. The front surface metal pattern has a slit, in a plan view, at a position away from a disposition region in which the sub-mount is disposed.

A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.

A semiconductor package device includes a substrate, a passive component, an active component and a package body. The passive component is disposed on the substrate. The active component is disposed on the substrate. The package body is disposed on the substrate. The package body includes a first portion covering the active component and the passive component, and a second portion covering the passive component. A top surface of the second portion of the package body is higher than a top surface of the first portion of the package body.