The present disclosure relates to a semiconductor package with a lid that includes a lid conductive structure. The semiconductor package includes a substrate with a top surface, a lid over the top surface of the substrate, and at least one substrate-mounted component mounted on the top surface of the substrate. Herein, a cavity is defined within the lid and over the top surface of the substrate. The substrate includes a metal pad over the top surface of the substrate. The lid includes a lid conductive structure, a lid body, and a perimeter wall that extends from a perimeter of the lid body toward the top surface of the substrate. The lid conductive structure includes a body conductor that extends through a portion of the lid body and a wall conductor that is coupled to the body conductor, extends through the perimeter wall, and is electronically coupled to the metal pad.

The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are operably coupled between an anode and a cathode. A set of primary bus lines are provided each being associated with a corresponding set of photosensitive cells. A secondary bus line is coupled to the set of primary bus lines. An electrical conductor is provided having a plurality of connection sites coupled to respective connection locations on the secondary bus line for providing conduction paths which have lower impedance than the secondary bus line.

A disclosed circuit arrangement includes a flexible substrate. A layer of pressure sensitive adhesive (PSA) is directly adhered to a first major surface of the substrate. One or more metal foil pads and electrically conductive wire are attached directly on a surface of the PSA layer. The wire has a round cross-section and one or more portions directly connected to the one or more metal foil pads with one or more weld joints, respectively. An electronic device is attached directly on the surface of the layer of PSA and is electrically connected to the one or more portions of the round wire by one or more bond wires, respectively.

Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.

A semiconductor device includes first and second semiconductor chips mounted on one package. In the first semiconductor chip, a current generation circuit generates a sense current in accordance with a load current and a fault current indicating that an abnormality detection circuit has detected an abnormality, and allows either one of the currents to flow through a current detecting resistor in accordance with presence or absence of detection of the abnormality. In the second semiconductor chip, a storage circuit stores a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value. An arithmetic processing circuit sets a standard range based on the determination reference value, and determines presence or absence of detection of the abnormality based on whether or not a current value indicated by a digital signal of an analog-digital conversion circuit is included within the standard range.

A method and device are provided wherein a first semiconductor device and a via are encapsulated with an encapsulant. A redistribution layer connects the first semiconductor device to a second semiconductor device. In a particular embodiment the first semiconductor device is an integrated voltage regulator and the second semiconductor device is a logic device such as a central processing unit.

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (first wires) extend from a surface of the substrate. Second wire bond wires (second wires) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

A converter includes a plurality of active circuitry elements over a substrate. The converter further includes a passivation structure over the plurality of active circuitry elements, the passivation structure having at least one opening that is configured to expose at least one electrical pad of each active circuitry element. The converter further includes a plurality of passive electrical components over the passivation structure, wherein each passive electrical component is selectively connectable with at least one other passive electrical component, and a first side of each passive electrical component is electrically coupled to an electrical pad of each of at least two active circuitry elements. The converter further includes a plurality of electrical connection structures, wherein a first electrical connection structure electrically couples an electrical pad of a first active circuitry element to a corresponding passive electrical component, and the first electrical connection structure is completely within the passivation structure.

The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are operably coupled between an anode and a cathode. A set of primary bus lines are provided each being associated with a corresponding set of photosensitive cells. A secondary bus line is coupled to the set of primary bus lines. An electrical conductor is provided having a plurality of connection sites coupled to respective connection locations on the secondary bus line for providing conduction paths which have lower impedance than the secondary bus line.

A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.