Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

The present disclosure relates to a semiconductor device that includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and each transistor including a gate electrode, a source electrode, and a drain electrode, a plurality of pads disposed on the semiconductor substrate and disposed at the outside of the plurality of transistors, a plurality of resistors disposed on the semiconductor substrate and electrically connected to the plurality of pads, respectively, and a plurality of upper metal layers disposed on the semiconductor substrate and configured to come into contact with the resistors. At least one of the plurality of resistors is an anti-resonance resistor that is disposed between two gate pads and is electrically connected to at least one gate pad of the two gate pads through the upper metal layer.

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper passive component pattern, and the second layer includes a lower passive component pattern, wherein the upper passive component pattern is opposite to the lower passive component pattern. The first interconnection layer includes at least one first interconnect structure electrically connected on the upper passive component pattern. The second interconnection layer includes at least one second interconnect structure electrically connected on the passive component pattern. The first interconnect structure on the upper passive component pattern is hybrid bonded with the second interconnect structure on the lower passive component pattern. Therefore, the upper passive component pattern and the lower passive component pattern are joined by hybrid bonding to form a passive device.

A voltage-controlled switching device includes a drain/drift structure formed in a semiconductor portion with a lateral cross-sectional area A.sub.Q, a source/emitter terminal, and an emitter channel region between the drain/drift structure and the source/emitter terminal. A resistive path electrically connects the source/emitter terminal and the emitter channel region. The resistive path has an electrical resistance of at least 0.1 mΩ*cm.sup.2/A.sub.Q.

A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.