A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.

A power semiconductor device module includes a metal baseplate and a plastic housing that together form a tray. Power electronics are disposed in the tray. A plastic cap covers the tray. Electrical press-fit terminals are disposed along the periphery of the tray. Each electrical terminal has a press-fit pin portion that sticks up through a hole in the cap. In addition, the module includes four mechanical corner press-fit anchors disposed outside the tray. One end of each anchor is embedded into the housing. The other end is an upwardly extending press-fit pin portion. The module is manufactured and sold with the press-fit pin portions of the electrical terminals and the mechanical corner anchors unattached to any printed circuit board (PCB). The mechanical anchors help to secure the module to a printed circuit board. Due to the anchors, screws or bolts are not needed to hold the module to the PCB.

In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network.

In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network.

An electronic device includes at least one chip and an insulating body embedding the chip. The electronic device further includes a heat-sink in contact with the chip. The heat-sink includes a plate having a first thickness. A recess is provided in the plate that defines a central portion of the plate having a second thickness less than the first thickness. The chip is mounted to the central region of the heat-sink within the recess. The insulating body includes a surface, such as a mounting surface, including an opening exposing at least a portion of the heat-sink. The device may further include a reophore extending through a side surface of the insulating body, that reophore being in contact with the heat sink.

An electronic device includes at least one chip and an insulating body embedding the chip. The electronic device further includes a heat-sink in contact with the chip. The heat-sink includes a plate having a first thickness. A recess is provided in the plate that defines a central portion of the plate having a second thickness less than the first thickness. The chip is mounted to the central region of the heat-sink within the recess. The insulating body includes a surface, such as a mounting surface, including an opening exposing at least a portion of the heat-sink. The device may further include a reophore extending through a side surface of the insulating body, that reophore being in contact with the heat sink.

Representative implementations of devices and techniques provide isolation between a carrier and a component mounted to the carrier. A multi-layer device having lateral elements provides electrical isolation at a preset isolation voltage while maintaining a preselected thermal conductivity between the component and the carrier.

Representative implementations of devices and techniques provide isolation between a carrier and a component mounted to the carrier. A multi-layer device having lateral elements provides electrical isolation at a preset isolation voltage while maintaining a preselected thermal conductivity between the component and the carrier.

A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first metallic clip (360) has a plate portion (360a) and a ridge portion (360c) bent at an angle from the plate portion. The plate portion is attached to the terminal of the first transistor chip opposite the second transistor chip. The ridge portion extends to the substrate is and is configured as a plurality of parallel straight fingers (360d). Each finger is discretely attached to the substrate using attachment material (361), for instance solder, and operable as a spring-line cantilever to accommodate, under a force lying in the plane of the substrate, elastic elongation based upon inherent material characteristics.

A switch circuit package module includes at least a semiconductor switch unit and at least a first capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element and the second semiconductor switch element include a plurality of sub micro-switch elements. The capacitor unit includes a plurality of capacitors configured to cooperate with the sub micro-switch elements. The capacitors are arranged in a symmetrical distribution surrounded the semiconductor switch unit, such that impedances of any two symmetrical commutation loops each of which mainly consists of one capacitor and two sub micro-switch elements from the first semiconductor switch element and second semiconductor switch element respectively are close to or the same with each other.