A switch circuit package module includes at least a semiconductor switch unit and at least a first capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element and the second semiconductor switch element include a plurality of sub micro-switch elements. The capacitor unit includes a plurality of capacitors configured to cooperate with the sub micro-switch elements. The capacitors are arranged in a symmetrical distribution surrounded the semiconductor switch unit, such that impedances of any two symmetrical commutation loops each of which mainly consists of one capacitor and two sub micro-switch elements from the first semiconductor switch element and second semiconductor switch element respectively are close to or the same with each other.

An electronic component, an optoelectronic component, a component arrangement, and a method for producing an electronic component are disclosed. In an embodiment, the method includes forming a sacrificial structure on a top side of a carrier by a photolithographic process from a photoresist layer, arranging an electronic semiconductor chip on the carrier after exposing the photoresist layer, molding a molded body around the sacrificial structure and around the electronic semiconductor chip such that a surface of the electronic semiconductor chip is at least partly not covered by the molded body, detaching the molded body from the carrier and removing the sacrificial structure, wherein removing the sacrificial structure results in a cutout being formed in the molded body.

A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.

A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.

A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.

In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.

A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

Inside an IGBT using GaN or SiC, light having an energy of approximately 3 [eV] is generated. Therefore, defects are caused in the gate insulating film of the IGBT. Furthermore, the charge trapped at a deep level becomes excited and moves to the channel region, thereby causing the gate threshold voltage to fluctuate from the predetermined value. Provided is a semiconductor device including a normally-ON semiconductor element that includes a first semiconductor layer capable of conductivity modulation and a first gate electrode, but does not include a gate insulating film between the first gate electrode and the first semiconductor layer; and a normally-OFF semiconductor element that includes a second semiconductor layer, a second gate electrode, and a gate insulating film between the second semiconductor layer and the second gate electrode. The normally-ON semiconductor element and the normally-OFF semiconductor element are connected in series.