H01L2924/141

Coaxial through via with novel high isolation cross coupling method for 3D integrated circuits

A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

Electronics card including multi-chip module

A method includes bonding a first package to a second package to form a third package. The first package is an Integrated Fan-Out (InFO) package including a plurality of package components, and an encapsulating material encapsulating the plurality of package components therein. The plurality of package components include device dies. The method further includes placing at least a portion of the third package into a recess in a Printed Circuit Board (PCB). The recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB. Wire bonding is performed to electrically connect the third package to the PCB.

Chip packages and methods for forming the same

A chip package for optical sensing includes a substrate, and a semiconductor device positioned on the substrate and coupled to the substrate through a first conducting element. Two molding processes are applied, to form a first colloid body on the substrate so as to cover the semiconductor device and, on the first colloid body, to form a second colloid body which covers an optical device. The optical device is electrically connected to the substrate through a second conducting element. The light transmittance of the second colloid body exceeds that of the first colloid body.

Methods for producing packaged semiconductor devices

A method comprises: arranging a plurality of semiconductor chips above a carrier, wherein active main surfaces of the semiconductor chips face the carrier; filling a cavity with a molding material; pressing the semiconductor chips arranged on the carrier into the molding material; and separating the molding material with the semiconductor chips embedded therein from the carrier, wherein main surfaces of the semiconductor chips that are situated opposite the active main surfaces are covered by the molding material.

Semiconductor structure and method for forming thereof

A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes the following operations. A first integrated circuit component having a fuse structure is received. A second integrated circuit component having an inductor is received. The second integrated circuit component is bonded to the first integrated circuit component. The inductor is electrically connected to the fuse structure, wherein the inductor is electrically connected to a ground through the fuse structure.

Warpage Control of Packages Using Embedded Core Frame
20210035877 · 2021-02-04 ·

A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

Fingerprint sensor pixel array and methods of forming same

A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.

Die stack structure and method of fabricating the same

Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 m per 1 mm range. A method of manufacturing the die stack structure is also provided.

Die stack structure and method of fabricating the same

Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 m per 1 mm range. A method of manufacturing the die stack structure is also provided.

Semiconductor Package and Method for Fabricating a Semiconductor Package
20200395266 · 2020-12-17 ·

A semiconductor package for double sided cooling includes a first and a second carrier facing each other, at least one power semiconductor chip arranged between the first and second carriers, external contacts arranged at least partially between the first and second carriers, and spring elements arranged between the first and second carriers and configured to keep the first and second carriers at a predefined distance from each other.