A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.

A method includes bonding a first package to a second package to form a third package. The first package is an Integrated Fan-Out (InFO) package including a plurality of package components, and an encapsulating material encapsulating the plurality of package components therein. The plurality of package components include device dies. The method further includes placing at least a portion of the third package into a recess in a Printed Circuit Board (PCB). The recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB. Wire bonding is performed to electrically connect the third package to the PCB.

Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

A device includes an outer seal ring, an integrated circuit, and an inner seal ring. The outer seal ring forms a first closed loop. The integrated circuit is surrounded by the outer seal ring. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring forms a second closed loop that defines an enclosed region external to the integrated circuit.

A method of manufacturing a package is disclosed. In one example, the method comprises applying a metallic connection structure, which comprises a solder or sinter material, on a sacrificial carrier. An electronic component is mounted on the metallic connection structure. At least part of the electronic component and of the metallic connection structure is encapsulated. Thereafter, the sacrificial carrier is removed to thereby expose at least part of the metallic connection structure.

An electronic device includes a substrate, a base substrate, a metal connection body, a support body, a metal body, and a via. The substrate includes one main surface with a functional element and is a piezoelectric substrate or a compound semiconductor substrate. The substrate is mounted on the base substrate such that the one main surface faces the base substrate. The metal body is in contact with the support body and includes at least a portion extending to outside the substrate in plan view from the support body. The via connects the portion of the metal body outside the substrate and the base substrate to each other and has a higher thermal conductivity than the substrate.

An electronic device includes a substrate, a base substrate, a metal connection body, a metal body, and a via. The substrate includes a first main surface provided with functional elements and is a piezoelectric substrate or a compound semiconductor substrate. The substrate is mounted on the base substrate such that a second main surface of the substrate opposite to the one main surface faces the base substrate. The metal body is provided at the first main surface of the substrate and includes at least a portion that extends to outside the substrate in plan view from the one main surface. The via connects the portion of the metal body outside the substrate and the base substrate to each other and has a higher thermal conductivity than the substrate.