A manufacturing method of a semiconductor device includes mounting a semiconductor element on a first electrode disposed on a first surface of a substrate; preparing a metal plate including a main body part and a projection part; mounting the metal plate on the first surface side of the substrate, by joining the projection part to a second electrode that is disposed on the first surface of the substrate; sealing the semiconductor element and the projection part with a sealing resin; and forming an electrode terminal made of a base end part that is connected to the second electrode and has a side surface that is covered by the sealing resin, and a tip end part that is integrally formed with the base end part and that projects from a front surface of the sealing resin, by etching the main body part excluding a portion overlapping with the projection part.

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.

A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

A wireless IC device includes a resin member including first and second surfaces, a substrate including first and second principal surfaces, a coil antenna provided in the resin member, and an RFIC element mounted on the substrate and connected to the coil antenna. The substrate is embedded in the resin member so that the second principal surface is at a second surface side. The coil antenna is defined by first linear conductor patterns on the second surface, first metal posts extending between the first and second surfaces, second metal posts extending between the first and second surfaces, and second linear conductor patterns on the first surface. The RFIC element is disposed in the coil antenna.

A semiconductor package structure includes a substrate structure having a first surface and a second surface opposite to the first surface; at least two electronic components electrically connected to the first surface of the substrate structure; at least one shielding pad disposed on the first surface of the substrate structure; a plurality of vias connected to the at least one shielding pad; a plurality of shielding wirebonds disposed between the electronic components. Each of the shielding wirebonds includes a first bond and a second bond opposite to the first bond, the first bond and the second bond being electrically connected to the at least one shielding pad, and the vias being free from overlapping with any of the plurality of vias.

An electronic component includes a metal member, an inductor, and a encapsulating resin. The metal member has an outer lead, an inner lead provided at a position opposed to the outer lead, and a post connecting the outer lead with the inner lead. The inductor is provided between the outer lead and the inner lead and connected to the outer lead or the inner lead. The encapsulating resin encapsulates the metal member and the inductor.

A manufacturing method of a semiconductor device includes mounting a semiconductor element on a first electrode disposed on a first surface of a substrate; preparing a metal plate including a main body part and a projection part; mounting the metal plate on the first surface side of the substrate, by joining the projection part to a second electrode that is disposed on the first surface of the substrate; sealing the semiconductor element and the projection part with a sealing resin; and forming an electrode terminal made of a base end part that is connected to the second electrode and has a side surface that is covered by the sealing resin, and a tip end part that is integrally formed with the base end part and that projects from a front surface of the sealing resin, by etching the main body part excluding a portion overlapping with the projection part.

A device includes a first die including a pseudo-random binary sequence (PRBS) generator that outputs test signals on parallel lanes. The device further includes a second die comprising a PRBS checker that compares at least a portion of the test signals with reference signals to identify a particular lane associated with an error.