Patent classifications
H01L2924/15786
OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE
An oscillator includes a vibration element, an oscillation circuit configured to oscillate the vibration element and output an oscillation signal, a temperature sensor, a temperature compensation circuit configured to compensate for a frequency temperature characteristic of the vibration element based on an output signal of the temperature sensor. The vibration element is within a first case having a first atmosphere, and the oscillation circuit, the temperature sensor, and the first case are within a second case having a second atmosphere, whereby the first atmosphere has a higher thermal conductivity than the second atmosphere.
Through-hole electrode substrate
A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.
Component carrier assembly having a trench structure which separates component carrier regions, and method for producing a plurality of component carrier regions
A component carrier assembly (1) is provided which has a plurality of component carrier regions (10), which are intended for mounting semiconductor components. The component carrier assembly comprises a carrier body (2) with a first major face (21). On the first major face a trench pattern (3) is formed in the carrier body, with first trenches (31) extending parallel to one another in a first direction, the first trenches delimiting the component carrier regions in a second direction extending transversely of the trenches. A coating (4) is formed on the carrier body, such that the component carrier regions each have a first major face of the carrier body which is coated at least in places and a side face (5) of the trench pattern which is coated at least in places.
Thermally-enhanced provision of underfill to electronic devices using a stencil
A method of feeding underfill material to fill a space between a semiconductor die and a substrate onto which the semiconductor die has been bonded, the method comprises positioning a stencil over the semiconductor die. The stencil has an elongated slot extending adjacent to an edge of the semiconductor die. Underfill material is printed through the slot such that the underfill material falls through the slot onto the substrate next to the edge of the semiconductor die. Thereafter, the underfill material is heated such that the underfill material flows across the space between the semiconductor die and the substrate from the edge of the semiconductor die to an opposite edge thereof through capillary action.
MULTI-INTERPOSER STRUCTURES AND METHODS OF MAKING THE SAME
Various disclosed embodiments include a substrate, a first interposer coupled to the substrate and to a first semiconductor device die, and a second interposer coupled to the substrate and to a second semiconductor device die. The first semiconductor device die may be a serializer/de-serializer die and the first semiconductor device die coupled to the first interposer may be located proximate to a sidewall of the substrate. In certain embodiments, the second semiconductor device die may be a system-on-chip die. In further embodiments, the second interposer may also be coupled to high bandwidth memory die. Placing a serializer/de-serializer die proximate to a sidewall of a substrate allows a length of electrical pathways to be reduced, thus reducing impedance and RC delay. The use of smaller, separate, interposers also reduces complexity of fabrication of interposers and similarly lowers impedance associated with redistribution interconnect structures associated with the interposers.