A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second level includes an array of memory cells, and where each of the memory cells includes at least one recessed-channel-array-transistor (RCAT).

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; second metal layer overlaying the first metal layer, and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include a High-k metal gate, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A semiconductor device, the device including: a first single crystal substrate and plurality of logic circuits, where the first single crystal substrate has a device area, where the device area is significantly larger than a reticle size, where the plurality of logic circuits include an array of processors, where the plurality of logic circuits include a first logic circuit, a second logic circuit, and third logic circuit, where the plurality of logic circuits include switching circuits to support replacing the first logic circuit and the second logic circuit by the third logic circuit; and a built-in-test-circuit (“BIST”), where the built-in-test-circuit is connected to test at least the first logic circuit and the second logic circuit.

A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least one metal layer, where the at least one metal layer interconnecting the first transistors; a plurality of logic gates including the at least one metal layer interconnecting the first transistors; a plurality of second transistors atop the at least one metal layer; a plurality of third transistors atop the second transistors; a top metal layer atop the third transistors; and a memory array including wordlines, where the memory array includes at least two rows by two columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second transistors or at least one of the third transistors.

An interposer sandwich structure includes a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes an attachment for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.

A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.

A method for producing a 3D memory device, the method comprising: providing a first level comprising a first single crystal layer; forming first alignment marks and control circuits comprising first single crystal transistors, wherein said control circuits comprise at least two metal layers; forming at least one second level above said control circuits; performing a first etch step within said second level; forming at least one third level above said at least one second level; performing a second etch step within said third level; and performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein said first etch step comprises performing a lithography step aligned to said first alignment marks.

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the bonded includes metal to metal bonds, where the second level includes an array of memory cells, and where each of the memory cells includes at least one recessed-channel-array-transistor (RCAT).