A semiconductor device is made by calculating a thermal resistance matrix for the semiconductor device. A plurality of maximum junction temperatures for the plurality of die of the semiconductor device is selected. A plurality of power envelope surfaces are calculated for the semiconductor device based on the thermal resistance matrix and the maximum junction temperatures. A plurality of powers is selected for the plurality of die. The plurality of powers are compared against the plurality of power envelope surfaces to determine a plurality of risk values.

In an embodiment, a package is provided. The package includes a semiconductor device; an encapsulant laterally surrounding the semiconductor device; and a heat dissipation structure disposed over the semiconductor device and the encapsulant, wherein the heat dissipation structure includes a plurality of pillars and a porous layer extending over sidewalls of the plurality of pillars.

Various applications of interconnect substrates in power management systems are described.

The system and method for a heterogeneous integrated circuit packaging method having an air-cavity lid to protect the active face of an integrated circuit, or other device, either active or passive, from the environment. The packaging is hermetic or near hermetic. In some examples, the cover provides electrical routing. In some examples, the cover also provides electromagnetic shielding. In some cases, an encapsulant and/or an overmoulding is provided to further protect the heterogeneous integrated circuit.

In a described example, an electrical apparatus includes a substrate having a first surface and lead pads on the first surface of the substrate for surface mounting components. A ribbon wire bond is provided having open ends and a central portion between the open ends, the open ends of the ribbon wire bond connected to the lead pads. An electrical component is bonded to the central portion of the ribbon wire bond. The central portion of the ribbon wire bond and the electrical component are spaced from the first surface of the substrate.

A device package includes a semiconductor device. The semiconductor device is disposed on a substrate. The device package further includes a covering. The covering is disposed on the substrate and surrounds the semiconductor device. The covering includes a void, a first layer, and a second layer. The void is between an interior surface of the covering and the semiconductor device. The first layer has a first electrical conductivity and a first thickness. The second layer is disposed under the first layer. The second layer has a second electrical conductivity and a second thickness. The first electrical conductivity is greater than the second electrical conductivity. The first thickness is less than the second thickness.

In a described example, an electrical apparatus includes a substrate having a first surface and lead pads on the first surface of the substrate for surface mounting components. A ribbon wire bond is provided having open ends and a central portion between the open ends, the open ends of the ribbon wire bond connected to the lead pads. An electrical component is bonded to the central portion of the ribbon wire bond. The central portion of the ribbon wire bond and the electrical component are spaced from the first surface of the substrate.

Various applications of interconnect substrates in power management systems are described.

An IC package including an IC and a TIM assembly located on the IC. The TIM assembly includes a lid defining a compartment, a mixed-phase material located in the compartment, the mixed-phase material including nanostructures, and a liquid metal occupying open spaces in the compartment that are not occupied by the nanostructures. A method of manufacturing an IC package, including providing the IC and placing the TIM assembly on the IC. A computer having one or more circuits that include the IC package.

A device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The package cover generally has an inlet opening and an outlet opening disposed there through. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package may include a material layer between the package cover and the cold plate. The cold plate may include a patterned first side and an opposite second side. The patterned first side may include a base surface and sidewalls extending downward from the base surface, where the base surface is spaced apart from the semiconductor device to collectively define a coolant channel. Here, the coolant channel is in fluid communication with the inlet opening and the outlet opening through openings disposed through respective portions of the material layer.