A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material.

The present invention relates to a molded air-cavity package. In addition, the present invention is related to a device comprising the same. The present invention is particularly related to molded air-cavity packages for radio-frequency ‘RF’ applications including but not limited to RF power amplifiers.

Instead of using hard-stop features that are arranged around the entire perimeter of the package in a continuous manner, the present invention proposes to use spaced apart pillars formed by first and second cover supporting elements. By using only a limited amount of pillars, e.g. three or four, the position of the cover relative to the body can be defined in a more predictable manner. This particularly holds if the pillars are arranged in the outer corners of the package.

A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.

Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.

A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.

The disclosure describes a lidded flip chip package allowing for a thermal interface material (TIM) with fluidity, like a liquid metal, including: a lid, a sealing ring for forming a sealed gap between a flip chip and the lid, a storage tunnel as a reservoir for accepting or releasing a liquid metal from or to the sealed gap, and an injection tunnel for filling a liquid metal into the sealed gap, wherein a self-sealing plug structure is integrated with the storage tunnel and the injection tunnel, the sealed gap is completely filled with a liquid metal, and a portion of the storage tunnel is filled with the same liquid metal and its remaining portion is filled with a gas. The disclosure also describes a method for filling a liquid metal into the lidded flip chip package based on the self-sealing plug structure.

A method includes: providing a package body including a mounting part having a chip mounting region for mounting a semiconductor chip, a side wall part having a first sealing surface continuously provided over an entire perimeter of the mounting part, surrounding the chip mounting region and provided on the mounting part, a first recess provided on the first sealing surface, and a first solder outflow prevention part continuously provided on the first sealing surface and positioned closer to the chip mounting region side than the first recess; providing a cap having a second sealing surface facing the first sealing surface; providing a ball solder made of an alloy of gold and tin as principal ingredients; placing the ball solder in the first recess; placing the cap on the ball solder; and melting once and then solidifying the ball solder to bond the first sealing surface and the second sealing surface.