Patent classifications
H01L2924/164
ELECTRONICS PACKAGE WITH IMPROVED THERMAL PERFORMANCE
An electronics package includes a thermal lid over a flip chip component such that the thermal lid is in contact with a surface of a flip chip component and one or more thermal vias in a substrate on which the flip chip component is mounted. The thermal lid dissipates heat from the flip chip component by way of the thermal vias to improve the thermal performance of the electronics package.
Electronics package with improved thermal performance
An electronics package includes a thermal lid over a flip chip component such that the thermal lid is in contact with a surface of a flip chip component and one or more thermal vias in a substrate on which the flip chip component is mounted. The thermal lid dissipates heat from the flip chip component by way of the thermal vias to improve the thermal performance of the electronics package.
System and Method for Bonding Package Lid
Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
System and method for bonding package lid
Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
COMPUTING DEVICES WITH AN ADHERED COVER AND METHODS OF MANUFACTURING THEREOF
A computing device is described. The computing device includes a support structure with an interface surface that has a cross-sectional width. The computing device includes a cover adhered to the interface surface of the support structure along an entirety of the cross-sectional width of the interface surface. A method of manufacturing a computing device is described. The method includes applying an adhesive to a cover. A support structure of a computing device is heated. The support structure is cooled. While the support structure is heated and cooled, pressure is applied to the cover.
Electronic component package structure and electronic device
An electronic component package structure includes at least a substrate having a set attachment area for attaching an electronic component; a conductive lid having a top and a sidewall that extends toward the substrate, where one side of the sidewall close to the substrate has a bonding end, where the bonding end bonds the conductive lid to the substrate by using a non-conductive adhesive, and the conductive lid bonded to the substrate encloses the attachment area and forms a shielding space over the attachment area; and the non-conductive adhesive is located between the substrate and the bonding end.
HERMETICALLY SEALED MEMS DEVICE AND ITS FABRICATION
In described examples, a hermetic package of a microelectromechanical system (MEMS) structure includes a substrate having a surface with a MEMS structure of a first height. The substrate is hermetically sealed to a cap forming a cavity over the MEMS structure. The cap is attached to the substrate surface by a vertical stack of metal layers adhering to the substrate surface and to the cap. The stack has a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance. The stack has: a first bottom metal seed film adhering to the substrate and a second bottom metal seed film adhering to the first bottom metal seed film; and a first top metal seed film adhering to the cap and a second top metal seed film adhering to the first top metal seed film.
SEMICONDUCTOR DEVICE PACKAGES AND METHOD OF MANUFACTURING THE SAME
A semiconductor device package includes a carrier, a lid, an electronic component and a sealant. The carrier has a first surface and a second surface opposite the first surface, and defines a hole extending from the first surface to the second surface. The lid is attached to the first surface of the carrier. The lid and the carrier define a chamber. The electronic component is attached to the first surface of the carrier and is disposed in the chamber. The sealant is attached to the second surface of the carrier and covers the hole.
Semiconductor package
A device (2) is formed on a main surface of a semiconductor substrate (1). A passivation film (5) covers the main surface. A metallized pattern (6) is formed on the passivation film (5) and surrounds the device (2). A sealing metal layer (7) is formed on the metallized pattern (6) and includes a corner portion (10) in a planar view. A lid (8) is bonded to the metallized pattern (6) with the sealing metal layer (7) interposed therebetween and vacuum-seals the device (2). A dummy wiring (11) is softer than the metallized pattern (6), is formed at least between an outer portion of the corner portion of the sealing metal layer (7) and the semiconductor substrate (1), and does not electrically connected to the device (2).
FAN-OUT PACKAGE STRUCTURE HAVING STACKED CARRIER SUBSTRATES AND METHOD FOR FORMING THE SAME
A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.