A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.

A chip package structure includes a substrate, a chip, an encapsulant, a plurality of solder balls and a patterned metal layer. The substrate includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the substrate. The encapsulant encapsulates the chip and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the substrate. The patterned metal layer s disposed on the encapsulant. The patterned metal layer includes at least one concave portion and at least one convex portion defined by the concave portion. The convex portion faces the encapsulant. The adhesion layer is disposed between the patterned metal layer and the encapsulant. The adhesion layer is filled in the concave portion.

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor element, a plurality of terminals, and a sealing resin. The semiconductor element has a front surface and a back surface. The front surface and the back surface face in opposite directions to each other in a thickness direction of the semiconductor element. The plurality of terminals are disposed at a distance from the semiconductor element and are electrically connected to the front surface. The sealing resin has a first surface facing in a same direction as the direction in which the front surface faces. Each of the plurality of terminals has a main surface exposed from the first surface.

An electronic element mounting substrate includes: a first wiring substrate configured to be a frame defining an interior portion as a first through-hole, the first wiring substrate including a lower surface including an external circuit connection electrode; a metal plate disposed on the lower surface of the first wiring substrate so as to cover an opening of the first through-hole, an outer edge thereof being located between an outer edge of the first wiring substrate and an inner edge of the first wiring substrate, an electronic element mounting portion being disposed in a region of an upper surface of the metal plate which region is surrounded by the first wiring substrate; and a second wiring substrate which is disposed in a peripheral region of the metal plate on the lower surface of the first wiring substrate and is electrically connected to the external circuit connection electrode.

An electronic element mounting substrate includes: a first wiring substrate configured to be a frame defining an interior portion as a first through-hole, the first wiring substrate including a lower surface including an external circuit connection electrode; a metal plate disposed on the lower surface of the first wiring substrate so as to cover an opening of the first through-hole, an outer edge thereof being located between an outer edge of the first wiring substrate and an inner edge of the first wiring substrate, an electronic element mounting portion being disposed in a region of an upper surface of the metal plate which region is surrounded by the first wiring substrate; and a second wiring substrate which is disposed in a peripheral region of the metal plate on the lower surface of the first wiring substrate and is electrically connected to the external circuit connection electrode.

A package structure includes a circuit substrate, a package unit, a thermal interface material and a cover. The package unit is disposed on and electrically connected with the circuit substrate. The package unit includes a first surface facing the circuit substrate and a second surface opposite to the first surface. A underfill is disposed between the package unit and the circuit substrate, surrounding the package unit and partially covering sidewalls of the package unit. The cover is disposed over the package unit and over the circuit substrate. An adhesive is disposed on the circuit substrate and between the cover and the circuit substrate. The thermal interface material includes a metal-type thermal interface material and is disposed between the cover and the package unit. The thermal interface material physically contacts the second surface and the sidewalls of the package unit and physically contacts the underfill.

The invention relates to a support and/or clip for at least one semiconductor element with at least one functional surface (10) for connecting to the semiconductor element. The invention is further characterized by at least one solder resist cavity (12) with at least one flank wall (13), in particular a straight flank wall (13), and a delimiting edge (14) which adjoins the flank wall (13) and delimits the functional surface (10) at least on one side. The delimiting edge (14) forms a protrusion (15) which protrudes past the functional surface (10) in order to retain solder, and/or the flank wall (13) forms an undercut (16) for retaining solder at the delimiting edge (14).

Electronic circuit packages are provided comprising: (a) at least one metal leadframe having a surface; (b) a surface treatment coating applied to the surface of the at least one metal leadframe to form at least one coated leadframe; and (c) an encapsulating polymeric layer that is molded over portions of the at least one coated leadframe. The surface treatment coating comprises: (1) a single-layer repellency coating applied to the surface of the at least one metal leadframe; or (2) a two-layer repellency coating comprising: (i) a first layer deposited from an aqueous solution of a metal salt, applied to the surface of the at least one metal leadframe; and (ii) a repellency layer applied to the first layer. Also provided are methods of reducing adhesion of mold flash from epoxy mold compound to a metal leadframe surface during manufacture of an electronic circuit package.

A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.