A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.

A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically connected to the first integrated circuit component. The third integrated circuit component is stacked on and electrically connected to the second integrated circuit component. The dielectric encapsulation laterally encapsulates the second integrated circuit component or the third integrated circuit component. In addition, manufacturing methods of the above-mentioned semiconductor device are provided.

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.

A semiconductor package includes an organic interposer, a semiconductor chip, a passivation layer, and an underbump metallurgy (UBM) layer. The organic interposer includes insulating layers and wiring layers disposed on the insulating layers. The semiconductor chip is disposed on one surface of the organic interposer. The passivation layer is disposed on another surface of the organic interposer opposing the one surface on which the semiconductor chip is disposed, and has openings extending to portions of the wiring layer. The UBM layer includes UBM pads disposed on the passivation layer and UBM vias disposed in the openings and connecting the UBM pads and the wiring layer to each other. At least one groove portion is disposed in an outer circumferential surface of the UBM pad.

Apparatuses for securing a memory card. One example apparatus can include a slot coupled to a printed circuit board (PCB), wherein the slot is configured to receive a memory card to provide electrical connection between the PCB and the memory card and a cover coupled to the PCB and configured to enclose the memory card when in a closed position and maintain electrical connection between the memory card and the PCB when in the closed position.

Apparatuses for securing a memory card. One example apparatus can include a slot coupled to a printed circuit board (PCB), wherein the slot is configured to receive a memory card to provide electrical connection between the PCB and the memory card and a cover coupled to the PCB and configured to enclose the memory card when in a closed position and maintain electrical connection between the memory card and the PCB when in the closed position.

A lead frame includes a first side having a first die attach pad that is bondable to a die, and a second side that has a second die attach pad that is bondable to another die. The lead frame includes multiple leads on the edges of the lead frame to connect the die. As part of a no-leads device, such as a quad flat no leads (QFN) or dual flat no-leads (DFN), one of the die attach pads is used in binding to a die, and the other die attach pad is used for thermal dissipation and mounting to a structure such as printed circuit board (PCB).

A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.