A semiconductor device comprising a stack of semiconductor chips. The semiconductor chips have an electrically active side and an opposite electrically inactive side. The active sides bordered by an edge having first lengths and the inactive sides bordered by a parallel edge having a second lengths smaller than the first lengths. A substrate has an assembly pad bordered by a linear edge having a third length equal to or smaller than the first lengths. The inactive chip side attached to the pad so that the edge of the first lengths are parallel to the edge of the third length. The active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first lengths.

Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads.

Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads.

A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.

An object is to provide technology that enables cost reduction or downsizing of semiconductor packages. The wiring element includes a second substrate, a plurality of first relay pads arranged on a surface of the second substrate opposite to the conductor substrate and connected to each of the control pads of the plurality of semiconductor elements by wires, a plurality of second relay pads arranged on the surface of the second substrate opposite to the conductor substrate, the number thereof being equal to or lower than the number of the plurality of first relay pads, and a plurality of wiring portions arranged on the surfaceof the second substrate opposite to the conductor substrate and selectively connecting the plurality of first relay pads and the plurality of second relay pads.

A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.

A semiconductor device includes: a chip unit, a conductive wire unit, and a cover unit. The chip unit includes a substrate formed with an interconnect structure, and a semiconductor chip disposed on the substrate. The conductive wire unit includes a conductive wire that interconnects the semiconductor chip and the interconnect structure. The cover unit includes a cover member that covers the conductive wire. The cover member includes an insulating layer formed by atomic layer deposition. A method for making the semiconductor device is also disclosed.

A semiconductor device has a leadframe and a first electrical component including a first surface disposed on the leadframe. A first clip bond is disposed over a second surface of the first electrical component. The first clip bond extends vertically through the semiconductor device. The first clip bond has a vertical member, horizontal member connected to the vertical member, die contact integrated with the horizontal member, and clip foot extending from the vertical member. A second electrical component has a first surface disposed on the first clip bond. A second clip bond is disposed over a second surface of the second electrical component opposite the first surface of the second electrical component. An encapsulant is deposited around the first electrical component and first clip bond. A second electrical component is disposed over the encapsulant. The clip foot is exposed from the encapsulant.

A semiconductor device according to an embodiment comprises a semiconductor element, a first terminal, a plurality of second terminals, and an encloser. The semiconductor element is rectangular. The first terminal has an upper surface to which a back surface of the semiconductor element is bonded. The second terminals are arranged around the first terminal. The second terminals are arranged at four corners of the encloser to be exposed from the bottom surface, and sides of the semiconductor element are opposed to the first side, the second side, the third side, and the fourth side, respectively. The first terminal is apart from the first side surface and the third side surface, a lower surface of the first terminal is exposed from the bottom surface, and the first terminal is partly exposed from the second side surface and the fourth side surface.

Provided is a semiconductor package. More particularly, the present invention relates to a clip, a lead frame, and a substrate used in a semiconductor package having engraved patterns formed on surfaces thereof so as to increase an adhesive force and a corrosion resistant performance, thereby improving reliability of the semiconductor package, and the semiconductor package including the same.