A first board includes a first ground plane, a first ground land, a first transmission line, and a first signal land connected to the first transmission line, wherein the first ground land and the first signal land are formed on the same surface. A second board includes a second ground plane, a second ground land, a second transmission line, and a second signal land connected to the second transmission line, wherein the second ground land and the second signal land are formed on a surface opposing the first board. The second ground land and the second signal land oppose the first ground land and the first signal land, respectively. A conduction member connects the first ground land and the second ground land. The first signal land and the second signal land are connected by capacitance coupling without using any conductor.

The wiring board has a first region overlapping a first semiconductor device and a second region not overlapping each of the first semiconductor device and a second semiconductor device. A first signal wiring of the wiring board has a first portion in the first region and a second portion in the second region. In a thickness direction of the wiring board, the second portion is between two ground patterns to which a reference potential is supplied, while the first portion has a portion not positioned between two ground patterns to which a reference potential is supplied. The first portion has a first wide portion having a larger width than a width of the second portion.

An electrical circuit device includes a circuit board including a cavity extending from a top surface of the circuit board to an embedded conductor, an integrated circuit chip in the cavity, an electrical connection between the integrated circuit chip and the embedded conductor, a thermal slug disposed over a top surface of the integrated circuit chip, and a heat sink mounted to an outer surface of the thermal slug for transferring a thermal energy away from the circuit board, the heat sink extending above a top surface of the circuit board.

A method of mounting an integrated circuit chip to a circuit board includes placing the integrated circuit chip into a cavity extending from a surface of the circuit board to an embedded conductor, and electrically connecting the integrated circuit chip to the embedded conductor.

An electrical circuit device that includes a circuit board with an integrated circuit chip in a cavity that extends from a surface of the circuit board to an embedded conductor, and an electrical connection between the integrated circuit chip and the embedded conductor.

A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.

A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.

Embodiments include package structures having integrated waveguides to enable high data rate communication between package components. For example, a package structure includes a package substrate having an integrated waveguide, and first and second integrated circuit chips mounted to the package substrate. The first integrated circuit chip is coupled to the integrated waveguide using a first transmission line to waveguide transition, and the second integrated circuit chip is coupled to the integrated waveguide using a second transmission line to waveguide transition. The first and second integrated circuit chips are configured to communicate by transmitting signals using the integrated waveguide within the package carrier.