The present disclosure provides a semiconductor structure including a first chip having a first dielectric surface, a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto, and an air gap between the second dielectric surface and the first dielectric surface. The first chip includes a plurality of first conductive lines in proximity to the first dielectric surface and parallel to each other, two adjacent first conductive lines each having a sidewall partially exposed from the first dielectric surface. The present disclosure further provides a method for manufacturing the semiconductor structure described herein.

A semiconductor structure includes a first dielectric waveguide, a second dielectric waveguide, a first inter-level dielectric (ILD) material, a first transmitter coupling structure and a second transmitter coupling structure. The first and second dielectric waveguides are disposed one over the other. The first dielectric waveguide is configured to guide a first electromagnetic signal. The second dielectric waveguide is configured to guide a second electromagnetic signal. The first and second electromagnetic signals have different frequencies. The first ILD material is disposed between the first and second dielectric waveguides. The first transmitter coupling structure is configured to couple a first driver signal generated by a transmitter die to the first dielectric waveguide, and accordingly produce the first electromagnetic signal. The second transmitter coupling structure is configured to couple a second driver signal generated by the transmitter die to the second dielectric waveguide, and accordingly produce the second electromagnetic signal.

Disclosed is a package for a semiconductor device including a semiconductor die. The package includes a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess in its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

The present technology relates to a semiconductor chip that can ensure a low impedance current path in an I/O ring while suppressing attenuation of radio frequency signals. The semiconductor chip includes: an I/O ring surrounding a core circuit; first and second pads serving as input/output terminals for radio frequency signals; and a radio frequency signal transmission line electrically connected to the first and second pads and the core circuit. The radio frequency signal transmission line is formed above the I/O ring. The present technology is applicable to a semiconductor chip that performs input and output of RF signals.

A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds while also facilitating single integrated designs compatible with tape implementation.

The present disclosure provides a semiconductor structure including a first chip having a first dielectric surface, a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto, and an air gap between the second dielectric surface and the first dielectric surface. The first chip includes a plurality of first conductive lines in proximity to the first dielectric surface and parallel to each other, two adjacent first conductive lines each having a sidewall partially exposed from the first dielectric surface. The present disclosure further provides a method for manufacturing the semiconductor structure described herein.

Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.

An antenna structure includes a radiative antenna element disposed in a first conductive layer, a reflector ground plane disposed in a second conductive layer under the first conductive layer, a feeding network comprising a transmission line disposed in a third conductive layer under the second conductive layer, and at least one coupling element disposed in proximity to a feeding terminal that electrically couples one end of the transmission line to the radiative antenna element. The coupling element is capacitively coupled with the feeding terminal.

A microwave antenna apparatus comprises a semiconductor package module comprising a mold layer, a semiconductor element, a coupling element and a redistribution layer, and an antenna module mounted on top of the semiconductor package module, said antenna module comprising an antenna substrate, one or more antenna elements, an antenna feed layer and an antenna ground layer. The footprint of the antenna module is larger than the footprint of the semiconductor package module.

A transition structure disposed in a package is disclosed. The transition structure comprises a first ground lead and a second ground lead; and a signal lead, disposed between the first ground lead and the second ground lead, wherein the first ground lead and the second ground lead have an exterior edge and an interior edge, the signal lead is coupled to a metal line formed on a printed circuit board (PCB) and a signal terminal of the die within the package; wherein an exterior gap formed between the first ground lead and the second ground lead at the exterior edge is wider than an interior gap formed between the first ground lead and the second ground lead at the interior edge.