The disclosure provides an electronic device which includes a substrate structure, a driving component, and a conductive pattern. The driving component and the conductive pattern are formed on the substrate structure, and the thickness of the conductive pattern is greater than or equal to 0.5 μm and less than or equal to 15 μm.

A package structure is provided. The package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conducive line, and a first conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. The first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.

A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate with a first surface and a second surface opposite to the first surface, a second substrate adjacent to the first surface of the first substrate, and an encapsulant encapsulating the first substrate and the second substrate. The first substrate defines a space. The second substrate covers the space. The second surface of the first substrate is exposed by the encapsulant. A surface of the encapsulant is coplanar with the second surface of the first substrate or protrudes beyond the second surface of the first substrate.

An electronic package in which at least one magnetically permeable member is disposed between a carrier and an electronic component, where the electronic component has a first conductive layer, and the carrier has a second conductive layer, such that the magnetically permeable element is located between the first conductive layer and the second conductive layer. Moreover, a plurality of conductive bumps that electrically connect the first conductive layer and the second conductive layer are arranged between the electronic component and the carrier to surround the magnetically permeable member for generating magnetic flux.

A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.

A substrate for a SIP is that has a portion of its top surface covered with spaced apart electrically conductive landing pads for electrical connection to components located on the surface and the landing pads serve as interconnection pads for making electrical connections between at least a portion of said pads when interconnected by a segment of bond wire to form at least a portion of the SIP. Methods for use of the universal substrate in SIP system design and manufacture of a SIP.

Embodiments are generally directed to module installation on printed circuit boards with embedded trace technology. An embodiment of a printed circuit board includes one or more layers including a top layer; multiple embedded traces that are contained in an area of a surface of a first layer of the one or more layers of the printed circuit board; and a first module, the first module being installed on the plurality of printed traces in the area.

It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

An antenna substrate includes: a first substrate including an antenna pattern disposed on an upper surface of the first substrate; a second substrate having a first planar surface, an area of which is smaller than an area of a planar surface of the first substrate; and a flexible substrate connecting the first and second substrates to each other and bent to allow the first planar surface of the second substrate to face a side surface of the first substrate, which is perpendicular to the upper surface of the first substrate.