A method of manufacturing an electronic package is disclosed. The described method includes (a) placing an electronic component on at least one layer structure; (b) encapsulating the electronic component by an encapsulant in a pressureless way; and (c) forming at least one further layer structure at the layer structure to thereby form a stack beneath the encapsulated electronic component. A further described electronic package includes (a) a stack comprising at least one layer structure and at least one further layer structure; (b) an electronic component being placed on the stack; and (c) an encapsulant encapsulating the electronic component, wherein the encapsulant has been formed in a pressureless way. Further described is an electronic device comprising such an electronic package.

The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.

A semiconductor die is disclosed, including circuitry comprising a transistor at a frontside of a semiconductor substrate, and a backside inductor at a backside of the semiconductor substrate. The backside inductor is electrically connected to the transistor of the circuitry.

Disclosed herein are antenna boards, integrated circuit (IC) packages, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an IC package having a die and a package substrate, and the package substrate has a recess therein; and an antenna patch, coupled to the package substrate, such that the antenna patch is over or at least partially in the recess.

In some embodiments, a surface-mountable device can include an electrical element and a plurality of terminals connected to the electrical element. The surface-mountable device can further include a body configured to support the electrical element and the plurality of terminals. The body can have a rectangular cuboid shape with a length, a width, and a height that is greater than the width. The body can include a base plane configured to allow surface mounting of the device.

An antenna apparatus includes a ground pattern having a through-hole; an antenna pattern disposed above the ground pattern and configured to either one or both of transmit and receive a radio-frequency (RF) signal; a feed via penetrating through the through-hole and having one end electrically connected to the antenna pattern; and a meta member comprising a plurality of cells repeatedly arranged and spaced apart from each other, each of the plurality of cells comprising a plurality of conductive patterns, and at least one conductive via electrically connecting the plurality of conductive patterns to each other, wherein the meta member is disposed along at least portions of side boundaries of the antenna pattern above the ground pattern, and extends above the antenna pattern.

A substrate having an electronic component embedded therein includes a core substrate including first and second wiring layers disposed on different levels and one or more insulating layers disposed between the first and second wiring layers, having a cavity in which a stopper layer is disposed on a bottom surface of the cavity, and including a groove disposed around the stopper layer on the bottom surface; an electronic component disposed on the stopper layer in the cavity; an insulating material covering at least a portion of each of the core substrate and the electronic component and disposed in at least a portion of each of the cavity and the groove; and a third wiring layer disposed on the insulating material. The stopper layer protrudes on the bottom surface.

A radio frequency module includes: a module board including first and second principal surfaces; first and second power amplifiers on the first principal surface; external-connection terminals on the second principal surface; and first and second via conductors connecting the first and second principal surfaces. The first and second via conductors are spaced apart in the module board, one end of the first via conductor is connected to a first ground electrode of the first power amplifier, the other end of the first via conductor is connected to a first external-connection terminal, one end of the second via conductor is connected to a second ground electrode of the second power amplifier, the other end of the second via conductor is connected to a second external-connection terminal, and the first and second via conductors each penetrate through the module board in a direction normal to the first and second principal surfaces.

A package structure includes a first semiconductor die, a second semiconductor die, a redistribution circuit structure, and a semiconductor device. The redistribution circuit structure has a first surface and a second surface opposite to the first surface, where the first surface is in contact with the first semiconductor die and the second semiconductor die, and the redistribution circuit structure is disposed on and electrically connected to the first semiconductor die and the second semiconductor die. The redistribution circuit structure includes a recess extending from the second surface toward the first surface. The semiconductor device is located in the recess and electrically connected to the first semiconductor die and the second semiconductor die through the redistribution circuit structure.