A semiconductor package includes a first connection structure having first and second surfaces and including a first redistribution layer, a first semiconductor chip disposed on the first surface and having a first connection pad electrically connected to the first redistribution layer, a second semiconductor chip disposed around the first semiconductor chip on the first surface and having a second connection pad electrically connected to the first redistribution layer, an interconnection bridge disposed on the second surface to be spaced apart from the second surface and connected to the first redistribution layer through a connection member to electrically connect the first and second connection pads to each other, and a second connection structure disposed on the second surface to embed the interconnection bridge and including a second redistribution layer electrically connected to the first redistribution layer.

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure being electrically connect to the integrated circuit die, the redistribution structure including a pad; a passive device including a conductive connector physically and electrically connected to the pad; and a protective structure disposed between the passive device and the redistribution structure, the protective structure surrounding the conductive connector, the protective structure including an epoxy flux, the protective structure having a void disposed therein.

This disclosure relates to deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted. In some aspects, a chip package includes an integrated circuit die that has a power distribution circuit for one or more circuits of the integrated circuit. The chip package also includes a substrate different from the integrated circuit and having a first surface on which the integrated circuit die is mounted and a second surface opposite the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to the power distribution circuit by conductors.

A radio frequency module includes a mounting substrate, a low-noise amplifier including an amplifying element and amplifying a radio frequency signal, and an impedance matching circuit including an integrated first inductor, in which the first inductor is connected to an input terminal of the low-noise amplifier, the low-noise amplifier and the impedance matching circuit are laminated in a direction perpendicular to a main surface of the mounting substrate, and a first multilayer body on which the low-noise amplifier and the impedance matching circuit are laminated is mounted on the main surface.

A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.

A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.

A substrate-on-substrate structure and an electronic device including the same are provided. The substrate-on-substrate structure includes: a first printed circuit board having a first side and a second side; a second printed circuit board disposed on the second side of the first printed circuit board, and having a first side connected to the second side of the first printed circuit board and a second side opposite to the first side connected to the second side of the first printed circuit board; a reinforcing structure attached to the first side of the second printed circuit board, and spaced apart from the second side of the first printed circuit board; and an underfill resin disposed between the second side of the first printed circuit board and the first side of the second printed circuit board, and covering at least a portion of the reinforcing structure.

A substrate-on-substrate structure and an electronic device including the same are provided, and the substrate-on-substrate structure includes: a first printed circuit board having a first side and a second side, opposite to the first side; a second printed circuit board disposed on the second side of the first printed circuit board, and having a first side connected to the second side of the first printed circuit board and a second side opposite to the first side connected to the second side of the first printed circuit board; a reinforcing structure attached to the first side of the second printed circuit board, and spaced apart from the second side of the first printed circuit board; and an underfill resin disposed between the second side of the first printed circuit board and the first side of the second printed circuit board, and covering at least a portion of the reinforcing structure.

A package structure includes a wiring structure, at least one electronic device, a reinforcement structure, a plurality of conductive vias and an encapsulant. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The electronic device is electrically connected to the wiring structure. The reinforcement structure is disposed on a surface of the wiring structure, and includes a thermoset material. The conductive vias is disposed in the reinforcement structure. The encapsulant covers the electronic device.

An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section. The second signal transmission path is between the second surface of the sub-computing section and the at least one conductive via of the sub-computing section.