A first signal electrode and a second signal electrode are connected by a first wire, a first ground electrode and a fourth ground electrode are connected by a second wire, and a second ground electrode and a third ground electrode are connected by a third wire. The second wire and the third wire cross at only one position above the first wire.

A reconstituted substrate, a packaged assembly comprising a reconstituted substrate, and methods for fabricating a reconstituted substrate. An example reconstituted substrate generally includes multiple package-level substrates implemented with different substrate technologies and held together. An example method for fabricating a reconstituted substrate generally includes forming multiple package-level substrates implemented with different substrate technologies, arranging the multiple package-level substrates, and adding a material to hold the multiple package-level substrates together.

Disclosed herein are capacitor-wirebond pad structures for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die and an IC package support. The IC package support may include a capacitor, and the capacitor may include a first capacitor plate, a second capacitor plate, and a capacitor dielectric between the first capacitor plate and the second capacitor plate. The die may be wirebonded to the first capacitor plate.

A transistor device structure may include a submount, a transistor device on the carrier submount, and a metal bonding layer between the submount and the transistor die, the metal bonding stack providing mechanical attachment of the transistor die to the submount. The metal bonding stack may include gold, tin and nickel. A weight percentage of a combination of nickel and tin in the metal bonding layer is greater than 50 percent and a weight percentage of gold in the metal bonding layer is less than 25 percent.

A package substrate may include a plurality of stacked insulation layers, a plurality of RDLs and a pair of impedance patterns. The RDLs may be arranged between the insulation layers. The impedance patterns may be arranged on an upper surface of at least one of the insulation layers. The impedance patterns may have an insulation length corresponding to a summed length of thicknesses of at least two insulation layers among the plurality of the insulation layers. Thus, a dummy conductive pattern may not be arranged between the impedance patterns and the RDL so that only the insulation layer may exist between the impedance patterns and the RDL. As a result, the insulation length of the impedance patterns may correspond to the summed length of the thicknesses of the at least two insulation layers.

A plurality of unit transistors that are connected in parallel to each other are formed on a substrate. In addition, a ground bump is provided on the substrate. A plurality of first capacitors are each provided for a corresponding one of the plurality of unit transistors and each connect an output electrode of the corresponding one of the plurality of unit transistors and the ground bump to each other.

A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.

A power amplifier includes a semiconductor die, and an amplifier and bias circuit integrally formed with the semiconductor die. The die has opposed first and second sides, and a device bisection line extends between the first and second sides. The bias circuit includes a multi-point input terminal with first and second terminals that are electrically connected through a conductive path that extends across the device bisection line, and one or more bias circuit components connected between the multi-point input terminal and the amplifier. The amplifier may include a field effect transistor (FET) with gate and drain terminals, and the bias circuit component(s) are electrically connected between the multi-point input terminal and the gate terminal. In addition or alternatively, the bias circuit component(s) are electrically connected between a multi-point input terminal and the drain terminal. The one or more components may include a resistor-divider circuit.

A novel and useful a single layer RFIC/MMIC structure including a package and related redistribution layer (RDL) based low loss grounded coplanar transmission line. The structure includes a package molded around an RF circuit die with a single redistribution layer (RDL) fabricated on the surface thereof mounted on an RF printed circuit board (PCB) via a plurality of solder balls. Coplanar transmission lines are fabricated on the RDL to conduct RF output signals from the die to PCB signal solder balls. The signal trace transition to the solder balls are funnel shaped to minimize insertion loss and maximize RF isolation between channels. A conductive ground shield is fabricated on the single RDL and operative to shield the plurality of coplanar transmission lines. The ground shield is electrically connected to a ground plane on the PCB via a plurality of ground solder balls arranged to surround the plurality of coplanar RF transmission lines and signal solder balls, and are operative to couple the ground shield to the ground plane on the PCB and provide an electrical return path for the plurality of coplanar transmission lines. Ground vias on the printed circuit board can be either located under the ground solder balls or between them.

A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.