A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

A semiconductor device includes a substrate, a semiconductor chip, and a sealing member. The semiconductor chip is disposed on the substrate. The semiconductor chip includes a first principal surface on a side of the substrate and a second principal surface on a side opposite to the first principal surface. The sealing member seals the semiconductor chip. The sealing member includes a first sealing member and a second sealing member. The second sealing member faces at least a part of the second principal surface. A permittivity of the second sealing member is lower than a permittivity of the first sealing member.

Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

A first chip includes a substrate, and first and second electrodes in a second region surrounding a first region. A second chip includes an interconnect layer, third and fourth electrodes in the second region, and first and second walls. Each of the first and third electrodes and the first wall includes a conductor surrounding the first region. The first and second electrodes are respectively in contact with the third and fourth electrodes. The first and second walls are in contact with the interconnect layer and are electrically coupled to the substrate via the first and third electrodes and the second and fourth electrodes, respectively. Each of a first ratio of an area covered by the first and second electrodes to the second region and a second ratio of an area of the third and fourth electrodes to the second region is 3% or more and 40% or less.

Multi-chip modules and methods of fabrication are described. The MCM may include a plurality of dies in which die-to-die routing can be partitioned within multiple metal routing layers for shorter die-to-die routings, while longer die-to-die routing can be routed primarily in a single metal routing layer. The plurality of dies may also be arranged in a spaced apart relationship to accommodate additional wiring area, while preserving direct routing areas for the longer die-to-die routing.

Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

A module and a substrate are provided in the present disclosure. The module includes an array substrate and a flexible circuit board. The array substrate includes a binding region including a first binding region and a second binding region; and in the binding region, the flexible circuit board is bound with the array substrate. In the first binding region, the array substrate includes a first conductive soldering pad; the flexible circuit board includes a second conductive soldering pad; and the first conductive soldering pad is electrically connected to the second conductive soldering pad. In the second binding region, the array substrate includes one or more of first soldering elements; the flexible circuit board includes one or more of second soldering elements; a first soldering element of the one or more of first soldering elements is fixed with a second soldering element of the one or more of second soldering elements.

A semiconductor device including: a first silicon layer including a first single crystal silicon and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, a connection path from the fifth metal layer to the second metal layer, where the connection path includes a via disposed through the second level, where the via has a diameter of less than 450 nm, where the fifth metal layer includes a global power distribution grid, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material has a first electrical conductivity before illumination of the material with optical radiation and a second electrical conductivity, different from the first electrical conductivity, after illumination of the material with optical radiation.