A package trace design technique provides at least partial cancelation of reflections. In one illustrative method of providing a high-bandwidth chip-to-chip link with a first die coupled to a second die via a first substrate trace, an intermediate trace, and a second substrate trace, the method includes: (a) determining a first propagation delay for an electrical signal to traverse the first substrate trace, the electrical signal having a predetermined symbol interval; (b) determining a second propagation delay for the electrical signal to traverse the second substrate trace; and (c) setting a length for at least one of the first and second substrate traces, the length yielding a difference between the first and second propagation delays, the difference having a magnitude equal to half the predetermined symbol interval.

The present disclosure relates to a package structure. The package structure includes a semiconductor device, a first molding compound, a through-via, first and second dielectric layers, and a second molding compound in contact with a sidewall of the first dielectric layer. The first molding compound is in contact with a sidewall of the semiconductor device. The through-via is formed in the first molding compound and electrically connected to the semiconductor device. The first and second dielectric layers are formed at upper and lower sides of the semiconductor device. The at least one redistribution line is formed in the first dielectric layer and electrically connected to the semiconductor device and the through-via. The second molding compound is in contact with a sidewall of the first dielectric layer. The at least one redistribution line comprises an ESD-protection feature or is a MIM (metal-insulator-metal) feature.

An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.

Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip including a reconstituted chip-level back endo of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic structures laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first and second vertically integrated electronic structures with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side opposite the first side; and removing material of the semiconductor carrier in a separation region between the first and second vertically integrated electronic structures to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first and second vertically integrated electronic structures remaining electrically connected with each other via the electrical connection layer.

A package structure is provided. The package structure includes a bottom die and a top die. The bottom die includes: a first active region surrounded by a first seal ring region; a first seal ring region including a bottom seal ring; and a first bonding layer disposed on a front side of the bottom die. The top die includes: a second active region surrounded by a second seal ring region; a second seal ring region including a top seal ring; and a second bonding layer disposed on a front side of the top die. The bottom die and the top die are bonded through hybrid bonding between the first bonding layer and the second bonding layer at an interface therebetween such that the bottom seal ring and the top seal ring are vertically aligned and are operable to form a continuous seal ring.

A package trace design technique provides at least partial cancelation of reflections. In one illustrative method of providing a high-bandwidth chip-to-chip link with a first die coupled to a second die via a first substrate trace, an intermediate trace, and a second substrate trace, the method includes: (a) determining a first propagation delay for an electrical signal to traverse the first substrate trace, the electrical signal having a predetermined symbol interval; (b) determining a second propagation delay for the electrical signal to traverse the second substrate trace; and (c) setting a length for at least one of the first and second substrate traces, the length yielding a difference between the first and second propagation delays, the difference having a magnitude equal to half the predetermined symbol interval.

An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.

A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.

An electronic device includes a first substrate structure, multiple electronic elements and a second substrate structure. The first substrate structure includes a first substrate. The electronic elements are disposed on the first substrate. The second substrate structure is coupled to the first substrate structure. The second substrate structure includes a second substrate, a protection circuit, a driving circuit and a bonding pad. The protection circuit is disposed on the second substrate. The driving circuit is disposed on the second substrate and configured to drive at least a part of the electronic elements. The bonding pad is disposed on the second substrate. The protection circuit is respectively coupled to the bonding pad and the driving circuit. The electronic device may reduce the damage caused by electrostatic discharge or reduce the impact of the bonding process of the bonding pad on signal conduction.