A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device includes a dielectric layer over the conductive pad, wherein the dielectric layer comprises silicon oxide. The semiconductor device includes a first passivation layer directly over the dielectric layer, wherein the first passivation layer comprises silicon oxide. The semiconductor device includes a second passivation layer directly over the first passivation layer, wherein the second passivation layer comprises silicon nitride.

Embodiments relate to a light-emitting diode package and a manufacturing method thereof and a light emitting device. The light-emitting diode package includes a lead frame comprising a substrate and leads formed on the substrate, a light-emitting diode chip mounted on the lead frame and electrically connected to the lead frame, an electrostatic discharge protection member mounted on the lead frame and electrically connected to the lead frame, a molding member comprising a wall surrounding components of the light-emitting diode package, the wall attached to the outer periphery of the lead frame, and the wall defining a cavity together with the lead frame, and a bead member covering a surface of the electrostatic discharge protection member, wherein the bead member comprising beads inducing diffuse reflection of light emitted from the light-emitting diode chip and incident on the electrostatic discharge protection member.

A semiconductor module includes a first semiconductor die, which comprises (i) a power support structure and (ii) a first cache region; and a second semiconductor die, which is mounted on top of the first semiconductor die and comprises (i) a logic core, which overlies and is electrically connected to the power support structure, and (ii) a second cache region, which overlies and is electrically connected to the first cache region.

The semiconductor package substrate module including a substrate, a plurality of first wires, at least one second wire, a chip, and an encapsulating body, wherein the first wires electrically connect to a first electrical contact point of the substrate and a second electrical contact point of the chip. Besides, one end of the at least one second wire connects to the at least one grounding transfer area or a first ground contact point of the substrate, and another end of the second wire extends toward a cutting area. The encapsulating body encapsulates the substrate, the first and second wires, and the chip. The semiconductor package substrate module is cut and separated along the cutting area of the substrate to form a plurality of semiconductor packaging components. A side surface of the encapsulating body exposes the first wires or at least one second wire of each semiconductor packaging component.

A semiconductor device includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip mounted on the first chip mounting portion, a second semiconductor chip mounted on the second chip mounting portion, a plurality of lead portions, and a sealing portion sealing them. The sealing portion has a first main surface and a second main surface opposite the first main surface. A groove portion is formed in the sealing portion at the first main surface. At the first main surface of the sealing portion, each of the first chip mounting portion and the second chip mounting portion is exposed from the sealing portion. At the first main surface of the sealing portion, the groove portion is formed between an exposed portion of the first chip mounting portion and an exposed portion of the second chip mounting portion.

A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device further includes a dielectric layer over the conductive pad, wherein the dielectric layer has a first conformity. The semiconductor device further includes a passivation layer over the dielectric layer, wherein the passivation layer has a second conformity different from the first conformity.

A method of making a semiconductor device includes depositing a dielectric layer over a conductive pad using a first deposition process. The method further includes depositing a first passivation layer directly over the dielectric layer using a high density plasma chemical vapor deposition (HDPCVD). The first deposition process is different from HDPCVD. A thickness of the dielectric layer is sufficient to prevent charges generated by depositing the first passivation layer from reaching the conductive pad.

The invention introduces a method for wire bonding and testing, performed by wire-bonding equipment, including at least the following steps: providing a substrate and dies, where the substrate has exposed fingers and each die has exposed pads; controlling a motor to hold the substrate by a metal frame, where all the exposed fingers are floating from the metal frame to avoid ESD (electrostatic discharge) fail; and performing a wire bonding to make interconnections between the pads on the dies and the fingers on the substrate to fabricate a semi-finished flash-memory product.

A light emitting device includes a resin package having a rectangular shape in a top view and two short-side lateral surfaces and two long-side lateral surfaces. The two short-side lateral surfaces include a first external surface and a second external surface located on an opposite side from the first external surface. The two long-side lateral surfaces include a third external surface and a fourth external lateral surface located on an opposite side from the third external lateral surface. The lead is not exposed on the third external lateral surface nor the fourth external lateral surface. The first lead is exposed at the first external lateral surface and the second external lateral surface, respectively flush with the resin member at the first external lateral surface and the second external lateral surface. The second lead is exposed at the second external lateral surface, flush with the resin part at the second external lateral surface.

Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type. Such a diode can be configured to turn on under selected conditions such as an ESD event. Such a structure can be configured so as to provide an effective ESD protection while providing little or substantially nil effect on radio-frequency (RF) operating properties of a device.