A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.

A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.

A semiconductor device includes a substrate, a package structure, a thermal interface material (TIM) structure, and a lid structure. The package structure is disposed on the substrate. The TIM structure is disposed on the package structure. The TIM structure includes a metallic TIM layer and a non-metallic TIM layer in contact with the metallic TIM layer, and the non-metallic TIM layer surrounds the metallic TIM layer. The lid structure is disposed on the substrate and the TIM structure.

A semiconductor package includes: a substrate structure having a first surface and an opposite second surface; a semiconductor chip on the first surface; and a connection bump on the second surface. The substrate structure includes: interconnection patterns disposed at different levels relative to the second surface; connection vias connecting the interconnection patterns; and a passivation layer covering a portion of the interconnection patterns and having an opening. The interconnection patterns include a first pattern and a second pattern, wherein the first pattern and the second pattern are adjacent to the second surface, and wherein a side surface of the first pattern faces a side surface of the second pattern. The second pattern includes a pad pattern and a metal layer in contact with the pad pattern and the connection bump. The first pattern has a first thickness and the second pattern has a pad thickness that is greater than the first thickness.

A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a second electronic component, and a reinforcement component. The reinforcement component is disposed above the first electronic component and the second electronic component. The reinforcement component is configured to reduce warpage.

A head includes: a head unit; and a wiring film configured to be connected to the head unit. The wiring film includes: a flexible substrate; a first IC provided on the flexible substrate; a second IC provided on the flexible substrate; a first wire provided on the flexible substrate to connect the first IC and a first contact portion of the head unit; a second wire provided on the flexible substrate to connect the second IC and a second contact portion of the head unit; and a third wire provided on the flexible substrate. The first IC has a long side extended in a predetermined direction and connected to the first wire, the second IC has a long side extended in the predetermined direction and connected to the second wire, and the first IC and the second IC are aligned along the predetermined direction to be apart from each other.

Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

A package structure is provided. The package structure includes a reinforced plate and multiple conductive structures penetrating through the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The package structure further includes multiple chip structures bonded to the redistribution structure through multiple solder bumps. In addition, the package structure includes a protective layer surrounding the chip structures.

The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.