A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.

Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.

A package substrate includes; a conductive line extending in a first horizontal direction, a conductive pad on an upper surface of the package substrate and horizontally spaced apart from the conductive line in a second horizontal direction, and a protective layer covering the conductive line and including an opening selectively exposing a portion of the conductive pad. The opening has an elongated elliptical shape having a minor axis defined by a width extending in the first horizontal direction and a major axis defined by a length extending in the second horizontal direction.

Before a semiconductor die of a brittle III-V compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.

A semiconductor device includes a semiconductor element, a joint material, a heat spreader, and a sealing resin. The semiconductor element includes a main surface. The main surface has a first outer periphery. The sealing resin seals the semiconductor element, the joint material, and the heat spreader. The heat spreader includes a main body and a protrusion. The protrusion is joined to the main surface by the joint material. The main surface has an exposed surface. The exposed surface is located between the first outer periphery and the joint material. The first outer periphery and the exposed surface are exposed from the joint material. The first outer periphery and the exposed surface are sealed with the sealing resin.

A semiconductor package includes a substrate; a semiconductor chip on a first surface of the substrate; and a plurality of external connection terminals on a second surface of the substrate that is opposite to the first surface. The substrate includes a plurality of wirings configured to electrically connect the semiconductor chip and the plurality of external connection terminals. The plurality of wirings includes a first wiring, and the first wiring includes a first portion and a second portion connected to each other, the second portion overlapping an edge of the semiconductor chip in a vertical direction that is perpendicular to the first surface of the substrate. A second width of the second portion is greater than a first width of the first portion.

A substrate for a semiconductor package includes an array of bonding pads on a first surface of the substrate, and a plurality of raised structures adjacent to at least some of the bonding pads on the first surface of the substrate. The raised structures may be configured to control the height of solder balls contacting the array of bonding pads when the package substrate is mounted onto a support substrate. The raised structures may compensate for a deformation of the package substrate so that the co-planarity of the solder balls may be improved, thereby providing an improved solder connection between the package substrate and the support substrate.

A power semiconductor module includes a substrate with a structured metallization layer and a number of semiconductor chips. Each chip has a first power electrode bonded to the metallization layer. A leadframe is laser-welded to second power electrodes of the semiconductor chips for electrically interconnecting the semiconductor chips. A control conductor is attached to the leadframe opposite to the semiconductor chips and is electrically isolated from the leadframe. The control conductor is electrically connected to control electrodes of the semiconductor chips in the group.

A package structure is provided. The package structure includes a redistribution structure and a semiconductor die over the redistribution structure, and bonding elements below the redistribution structure. The semiconductor die has a first sidewall and a second sidewall connected to each other. The bonding elements include a first row of bonding elements and a second row of bonding elements. In a plan view, the second row of bonding elements is arranged between the first row of bonding elements and an extending line of the second sidewall. A minimum distance between the second row of bonding elements and the first sidewall is greater than the minimum distance between the first row of bonding elements and the first sidewall.

A package structure is provided. The package structure includes a first conductive pad in an insulating layer, a first under bump metallurgy structure under the first insulating layer, and a first conductive via in the insulating layer. The first conductive via is vertically connected to the first conductive pad and the first under bump metallurgy structure. In a plan view, a first area of the first under bump metallurgy structure is confined within a second area of the first conductive pad.