Patent classifications
H01L2924/3841
Metal-bump sidewall protection
A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.
Semiconductor device manufacturing method
According to an embodiment, a temperature of an inside of a furnace is set to fall within a range of a reduction temperature or more of a carboxylic acid and less than a melting temperature of a solder bump, and the inside is concurrently set to have a first carboxylic acid gas concentration. Thereafter, the temperature of the inside is raised up to the melting temperature, and the inside is concurrently set to have a second carboxylic acid gas concentration. The second carboxylic acid gas concentration is lower than the first carboxylic acid gas concentration, and is a concentration containing a minimum amount of carboxylic acid gas defined to achieve reduction on an oxide film of the solder bump. The inside has the second carboxylic acid gas concentration at least at a time when the temperature of the inside reaches the melting temperature.
SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME
The present disclosure relates to the technical field of semiconductor packaging, and discloses a semiconductor structure and a method for forming the same. The method includes: providing a chip, the chip having interconnect structures on its surface, the top of the interconnect structures having an exposed fusible portion; providing a substrate, the substrate having conductive structures on its surface; patterning the conductive structures so that edges of the conductive structures have protrusions; combining the chip with the substrate. The new structure design avoids the product failure of the chip and the semiconductor substrate in the molding stage, and also strengthens the weld metal bonding force between the conductive structures and the substrate.
Bonded body and manufacturing method of bonded body
A bonded body includes: a first base body including a first wiring, a first electrode made of an electroplating film and including a first surface having a first region covering a periphery of an end portion of the first wiring and a second region covering the end portion of the first wiring, and a first passivation layer made of an insulating material and covering a periphery of the first electrode; a second base body including a second electrode; and solder disposed between the first region of the first electrode and the second electrode.
Bump-on-trace design for enlarge bump-to-trace distance
A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.
Method for forming package structure with a barrier layer
A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC.
SEMICONDUCTOR DEVICE, A PACKAGE SUBSTRATE, AND A SEMICONDUCTOR PACKAGE
A semiconductor device is provided. The semiconductor device includes a substrate, input and output (I/O) pads disposed at an upper portion of the semiconductor substrate, and first bump pillars disposed over the I/O pads. The first bump pillars are selectively arranged over some of the I/O pads in a first horizontal direction.
INTERCONNECT STRUCTURES AND SEMICONDUCTOR STRUCTURES FOR ASSEMBLY OF CRYOGENIC ELECTRONIC PACKAGES
A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures includes a substrate and a superconducting trace. Additionally, each of the semiconductor structures includes a passivation layer and one or more under bump metal (UBM) structures. The cryogenic electronic package also includes one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two superconducting semiconductor structures. The interconnect structures are electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures. A method of fabricating a cryogenic electronic package is also provided.
Semiconductor package and method for fabricating a semiconductor package
A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.
Semiconductor package
Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.