H01P3/082

Method of additively manufacturing an impedance transformer

A transmission line impedance transformer including at least two different dielectric media having different dielectric properties, each of the dielectric media being configured to taper in thickness along the length of the impedance transformer in an inverse relationship with respect to each other so as to form a combined dielectric medium having an effective dielectric property that is graded along the transmission path. The two or more dielectric media may be disposed between two conductors to provide an impedance transformer in which a characteristic impedance of the transmission line varies along its length in response to the gradation of the effective dielectric property of the combined dielectric medium.

Printed circuit boards and methods for manufacturing thereof for RF connectivity between electro-optic phase modulator and digital signal processor

A Printed Circuit Board (PCB) and methods for manufacturing the PCB board are provided. The PCB includes a Radio Frequency (RF) signal transition at a RF signal pad. Multiple conductive layers other than a conductive signal layer of the PCB and conductive portions of the conductive signal layer not in electrical contact with a RF signal transmission trace have common ground connections forming a ground cage structure within the PCB around the RF signal pad and RF the signal transmission trace.

TRANSMISSION LINE DEVICE
20200194859 · 2020-06-18 ·

A transmission line device includes first and second transmission lines. The first transmission line includes a first electrode pad that is electrically connected to a first signal conductor pattern, and a second electrode pad and a third electrode pad that are portions of a first ground conductor pattern. The second transmission line includes a fourth electrode pad that is electrically connected to a second signal conductor pattern, and a fifth electrode pad and a sixth electrode pad that are portions of a second ground conductor pattern. The first electrode pad is between the second electrode pad and the third electrode pad, and the fourth electrode pad is between the fifth electrode pad and the sixth electrode pad. The second electrode pad and the third electrode pad are larger than the first electrode pad, and the fifth electrode pad and the sixth electrode pad are larger than the fourth electrode pad.

Board-to-board interconnect apparatus including a microstrip circuit connected by a waveguide, where a bandwidth of a frequency band is adjustable

Disclosed is a chip-to-chip interface using a microstrip circuit and a dielectric waveguide. A board-to-board interconnection device, according to one embodiment of the present invention, comprises: a waveguide which has a metal cladding and transmits a signal from a transmitter-side board to a receiver-side board; and a microstrip circuit which is connected to the waveguide and has a microstrip-to-waveguide transition (MWT), wherein the microstrip circuit matches a microstrip line and the waveguide, adjusts the bandwidth of a predetermined first frequency band among the frequency bands of the signal, and provides same to the receiver.

Signal transmission line including a signal conductor and reinforcing conductor portions parallel to the signal conductor

A signal transmission line includes a laminate, a signal conductor, a hollow portion, and a reinforcing conductor. The laminate includes a flexible laminate including resin layers each of which has flexibility. The signal conductor extends in a signal transmission direction of the laminate and is disposed in an intermediate position in a laminating direction of the resin layers. The hollow portion is in the laminate and defined by an opening provided at a portion of the plurality of resin layers. The reinforcing conductor is in the laminate. The hollow portion is disposed at a position overlapping with the signal conductor, in a plan view of the laminate from a surface perpendicular or substantially perpendicular to the laminating direction. The reinforcing conductor is disposed at a position different from the position of the hollow portion in a plan view.

HIGH FREQUENCY FLEXIBLE FLAT CABLE
20200161733 · 2020-05-21 ·

A high frequency flexible flat cable includes a first metal isolation layer, a first low-k dielectric adhesive layer attached to one side of the first metal isolation layer, a second low-k dielectric adhesive layer attached another side of the first metal isolation layer and at least two conductor layers respectively attached to the first low-k dielectric adhesive layer and the second low-k dielectric adhesive layer. In addition, the high frequency flexible flat cable further includes a third low-k dielectric adhesive layer, a fourth low-k dielectric adhesive layer, a second metal isolation layer and a third metal isolation layer. The second metal isolation layer and the third metal isolation layer are respectively adhered to outsides of the conductor layers by using the third low-k dielectric adhesive layer and the fourth low-k dielectric adhesive layer to adjust the impedance of the high frequency flexible flat cable according to requirements.

Printed circuit boards and methods for manufacturing thereof for RF connectivity between electro-optic phase modulator and Digital Signal Processor

A Printed Circuit Board (PCB) and methods for manufacturing the PCB board are provided. The PCB includes a plurality of layers; a signal pad, at a first layer of the plurality of layers, connected to a signal transmission trace strip line, at a second layer of the plurality of layers, wherein the signal pad is configured to connect to a surface mount Radio Frequency (RF) connector that is configured to interface an RF signal with the signal pad; a PCB ground cage structure through the plurality of layers, surrounding the signal pad; and extended ground reference planes located at the first layer and a third layer of the plurality of layers, wherein the extended ground reference planes extend into a volume of the PCB ground cage structure.

SEMICONDUCTOR DEVICE INCLUDING TRANSMISSION LINES AND METHOD OF FORMING THE SAME
20200153073 · 2020-05-14 ·

A semiconductor device includes a first transmission line and a second transmission line. The semiconductor device further includes a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material surrounds the second transmission line. The semiconductor device further includes a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material is separated from the first transmission line and the second transmission line.

Packaged device including a transmission line associated with one of a conductive shield, vertical stubs, and vertically interdigitated stubs

Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

Multilayer substrate comprising a flexible element assembly and conductor layers
10644371 · 2020-05-05 · ·

A multilayer substrate includes an element assembly including stacked insulating layers and including at least a first insulating layer with a first principal surface and a second principal surface and a second insulating layer with a third principal surface and a fourth principal surface, a first conductor layer, and a second conductor layer. The second principal surface and the third principal surface are in contact with each other, and no planar or linear conductors are located on the second principal surface and the third principal surface. The first conductor layer is located on the first principal surface, and the second conductor layer is located on the fourth principal surface.