Technologies for providing accelerated functions as a service in a disaggregated architecture include a compute device that is to receive a request for an accelerated task. The task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task. The compute device is further to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request. Additionally, the compute device is to assign the task to the determined accelerator sled for execution. Other embodiments are also described and claimed.

A compute device to manage workflow to disaggregated computing resources is provided. The compute device comprises a compute engine receive a workload processing request, the workload processing request defined by at least one request parameter, determine at least one accelerator device capable of processing a workload in accordance with the at least one request parameter, transmit a workload to the at least one accelerator device, receive a work product produced by the at least one accelerator device from the workload, and provide the work product to an application.

Technologies for offloading acceleration task scheduling operations to accelerator sleds include a compute device to receive a request from a compute sled to accelerate the execution of a job, which includes a set of tasks. The compute device is also to analyze the request to generate metadata indicative of the tasks within the job, a type of acceleration associated with each task, and a data dependency between the tasks. Additionally the compute device is to send an availability request, including the metadata, to one or more micro-orchestrators of one or more accelerator sleds communicatively coupled to the compute device. The compute device is further to receive availability data from the one or more micro-orchestrators, indicative of which of the tasks the micro-orchestrator has accepted for acceleration on the associated accelerator sled. Additionally, the compute device is to assign the tasks to the one or more micro-orchestrators as a function of the availability data.

A cooking appliance includes sidewalls and a rear wall defining a heating cavity. At least one heat source is in thermal communication with the heating cavity. An oven cavity connector is disposed within an interior surface of the heating cavity. The oven cavity connector is in communication with the heating cavity. A first tray sliding structure is disposed proximate opposing vertical sidewalls of the heating cavity. A second tray sliding structure is disposed proximate the opposing vertical sidewalls and is vertically offset relative to the first tray sliding structure. A powered accessory tray has a connecting plug, the powered accessory tray being alternatively and selectively engaged with one of the first and second sliding tray structures, and the connecting plug is in selective communication with oven cavity connector when the powered accessory tray is engaged with any one of the first and second tray sliding structures.

Technologies for lifecycle management include multiple computing devices in communication with a lifecycle management server. On boot, a computing device loads a lightweight firmware boot environment. The lightweight firmware boot environment connects to the lifecycle management server and downloads one or more firmware images for controllers of the computing device. The controllers may include baseboard management controllers, network interface controllers, solid-state drive controllers, or other controllers. The lifecycle management server may select firmware images and/or versions of firmware images based on the controllers or the computing device. The computing device installs each firmware image to a controller memory device coupled to a controller, and in use, each controller accesses the firmware image in the controller memory device. The controller memory device may be a DRAM device or a high-performance byte-addressable non-volatile memory. Other embodiments are described and claimed.

A cooking appliance includes sidewalls and a rear wall defining a heating cavity. At least one heat source is in thermal communication with the heating cavity. An oven cavity connector is disposed within an interior surface of the heating cavity. The oven cavity connector is in communication with the heating cavity. A first tray sliding structure is disposed proximate opposing vertical sidewalls of the heating cavity. A second tray sliding structure is disposed proximate the opposing vertical sidewalls and is vertically offset relative to the first tray sliding structure. A powered accessory tray has a connecting plug, the powered accessory tray being alternatively and selectively engaged with one of the first and second sliding tray structures, and the connecting plug is in selective communication with oven cavity connector when the powered accessory tray is engaged with any one of the first and second tray sliding structures.

Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.

Technologies for dynamically managing the reliability of disaggregated resources in a managed node include a resource manager server. The resource manager server includes communication circuit to receive resource data from a set of disaggregated resources that indicates reliability of each disaggregated resource of the set of disaggregated resources and a node request to compose a managed node. The resource manager server further includes a compute engine to determine node parameters from the node request indicative of a target reliability of one or more disaggregated resources of the set of disaggregated resources to be included in the managed node, compose a managed node from the set of disaggregated resources that satisfies the node parameters by configuring the compute sled to utilize the disaggregated resources of the managed node for the execution of a workload, and monitor the disaggregated resources of the managed node for a failure.

A data connector to interface with a sled of a data center includes a main body, a plurality of guide shafts, and a cover. The main body includes electrical contacts. The guide shafts are associated with the main body, and each guide shaft extends along a corresponding longitudinal axis. The cover is coupled to the guide shafts such that the cover is slidable along the guide shafts in a direction defined by the longitudinal axes. The cover includes a movable door to provide protection to the electrical contacts of the main body when not in use.

Technologies for lifecycle management include multiple computing devices in communication with a lifecycle management server. On boot, a computing device loads a lightweight firmware boot environment. The lightweight firmware boot environment connects to the lifecycle management server and downloads one or more firmware images for controllers of the computing device. The controllers may include baseboard management controllers, network interface controllers, solid-state drive controllers, or other controllers. The lifecycle management server may select firmware images and/or versions of firmware images based on the controllers or the computing device. The computing device installs each firmware image to a controller memory device coupled to a controller, and in use, each controller accesses the firmware image in the controller memory device. The controller memory device may be a DRAM device or a high-performance byte-addressable non-volatile memory. Other embodiments are described and claimed.