The present disclosure relates to an electronic device comprising a wafer comprising a first upper surface having at least one first contact arranged thereon; and at least one die comprising a second upper surface having at least one second contact arranged thereon, and at least one first lateral surface orthogonal to the second upper surface, said first contact being coupled to said second contact by a connector comprising one first conductive pillar formed on said first contact of said wafer; one second conductive pillar formed on said second contact of said die; and at least one conductive ball positioned in contact with at least a first upper portion of said first pillar(s) and in contact with at least one second upper portion of said second pillar(s).

A semiconductor surface-emitting laser array can be provided with a group of independently addressable light-emitting pixels arranged in at least two rows and in a linear array on a common substrate chip and including a common cathode and a dedicated channel associated with an address trace line for each pixel. An aggregate linear pitch can be achieved between pixels of the at least two rows along the linear array in a cross process direction that is less than the size of a pixel. The semiconductor laser array can include more than one common substrate chip tiled and stitched together in a staggered arrangement to provide an at least 11-inch wide, 1200pdi imager with timing delays associated with each of the more than one common substrate chip in the staggered arrangement.

A semiconductor surface-emitting laser array can be provided with a group of independently addressable light-emitting pixels arranged in at least two rows and in a linear array on a common substrate chip and including a common cathode and a dedicated channel associated with an address trace line for each pixel. An aggregate linear pitch can be achieved between pixels of the at least two rows along the linear array in a cross process direction that is less than the size of a pixel. The semiconductor laser array can include more than one common substrate chip tiled and stitched together in a staggered arrangement to provide an at least 11-inch wide, 1200pdi imager with timing delays associated with each of the more than one common substrate chip in the staggered arrangement.

A 3D package for semiconductor thermal management can include a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept cooling liquid therethrough, a first tubular connection for providing cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel. Integrated slots can be provided for accepting and mounting semiconductor components. Mounting holes can be formed in the mechanical block for securing optical elements. At least one semiconductor laser array die can be secured to the mechanical block at the integrated slots, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel.

A 3D package for semiconductor thermal management can include a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept cooling liquid therethrough, a first tubular connection for providing cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel. Integrated slots can be provided for accepting and mounting semiconductor components. Mounting holes can be formed in the mechanical block for securing optical elements. At least one semiconductor laser array die can be secured to the mechanical block at the integrated slots, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel.

In some implementations, an opto-electrical device includes a heatsink; a thermally conductive element disposed on a first region of a surface of the heatsink; an adaptive thickness thermally conductive pad disposed on the thermally conductive element; an integrated circuit (IC) disposed on the adaptive thickness thermally conductive pad; a thermoelectric cooler (TEC) disposed on a second region of the surface of the heatsink; an opto-electrical chip disposed on the TEC; and a substrate disposed on the IC and the opto-electrical chip, wherein the substrate is configured to electrically connect the IC and the opto-electrical chip.

In some implementations, an opto-electrical device includes a heatsink; a thermally conductive element disposed on a first region of a surface of the heatsink; an adaptive thickness thermally conductive pad disposed on the thermally conductive element; an integrated circuit (IC) disposed on the adaptive thickness thermally conductive pad; a thermoelectric cooler (TEC) disposed on a second region of the surface of the heatsink; an opto-electrical chip disposed on the TEC; and a substrate disposed on the IC and the opto-electrical chip, wherein the substrate is configured to electrically connect the IC and the opto-electrical chip.

A computer adapted to convert images into raw data can provide the raw data to a control interface adapted to transmit the raw data with timing information to an electronic driver circuit. The electronic driver circuit can convert the raw data with the timing information provided by a control interface into regulated current signals provided to the semiconductor laser array at 300 dpi and higher. The semiconductor array can convert the current signals into light to illuminate an imaging member. The laser array can comprise vertical cavity surface emitting lasers providing imaging greater than 300 dpi. Each semiconductor laser can operate at 50 mW or greater.

A method of transferring a semiconductor epi layer onto a metal host substrate is described. An epi layer of a semiconductor chip (e.g., semiconductor laser array) including a substrate can be mounted onto a planar handle wafer with an adhesive, wherein a backside of the substrate faces upward and away from the epi layer and the planar handle wafer. The backside of the substrate can be treated to substantially remove the substrate, while leaving the epi layer undamaged (e.g., by polishing to where no more than 20 micrometers of the substrate remains). Metal can be formed on the treated backside resulting in a metalized backside. The planar handle wafer can then be removed from the epi layer by dissolving the adhesive with a solvent, wherein a modified semiconductor chip remains. The semiconductor chip can be annealed to form a backside ohmic contact interface. The semiconductor chip can then be attached to a mechanical block by the ohmic contact interface.

Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad. First conductive pad is connected to through semiconductor via. Emission region directly faces sidewall of recess where edge coupler is located.