A device includes a first cladding layer, a waveguide laser, an absorption layer, and a second cladding layer. The absorption layer is constituted by an oversaturation absorption body such as graphene. Also, the absorption layer is provided between the active layer and the distributed Bragg reflection portion. The absorption layer is formed below a core forming an optical waveguide between the active layer and a distributed Bragg reflection portion.

The invention relates to a semiconductor laser comprising a layer structure comprising an active zone, wherein the active zone is configured to generate an electromagnetic radiation, wherein the layer structure comprises a sequence of layers, wherein two opposite end faces are provided in a Z-direction, wherein at least one end face is configured to at least partly couple out the electromagnetic radiation, and wherein the second end face is configured to at least partly reflect the electromagnetic radiation, wherein guide means are provided for forming an optical mode in a mode space between the end faces, wherein means are provided which hinder a formation of an optical mode outside the mode space, in particular modes comprising a propagation direction which do not extend perpendicularly to the end faces.

The invention relates to an edge-emitting semiconductor laser diode, having: —a semiconductor layer sequence, which comprises a bottom surface, a ridge waveguide on a top surface facing away from the bottom surface, and a side surface which is arranged transverse to the top surface, and —a first recess, which extends from the bottom surface to the top surface, wherein —a first region of the semiconductor layer sequence is removed from the side surface in the region of the first recess. The invention further relates to a method for producing a plurality of edge-emitting semiconductor laser diodes.

A semiconductor optical device includes: a laser for emitting light; a modulator for modulating the light using an electroabsorption effect; a chip capacitor that is electrically connected in parallel to the laser; a chip inductor that is electrically connected in series to the chip capacitor, is electrically connected in series to the laser and the chip capacitor as a whole, and includes a first terminal and a second terminal; a solder or a conductive adhesive that directly bonds the first terminal of the chip inductor and the chip capacitor to each other; an electrical wiring group in which the laser, the modulator, the chip capacitor, and the chip inductor are electrically connected to each other; and a substrate on which the laser, the modulator, the chip capacitor, and the chip inductor are mounted.

A method for improving wide-band wavelength-tunable laser. The method includes configuring a gain region between a first facet and a second facet and crosswise a PN-junction with an active layer between P-type cladding layer and N-type cladding layer. The method further includes coupling a light excited in the active layer and partially reflected from the second facet to pass through the first facet to a wavelength tuner configured to generate a joint interference spectrum with multiple modes separated by a joint-free-spectral-range (JFSR). Additionally, the method includes configuring the second facet to have reduced reflectivity for increasing wavelengths. Furthermore, the method includes reconfiguring the gain chip with an absorption layer near the active layer to induce a gain loss for wavelengths shorter than a longest wavelength associated with a short-wavelength side mode. Moreover, the method includes outputting amplified light at a basic mode via the second facet.

A method for improving wide-band wavelength-tunable laser. The method includes configuring a gain region between a first facet and a second facet and crosswise a PN-junction with an active layer between P-type cladding layer and N-type cladding layer. The method further includes coupling a light excited in the active layer and partially reflected from the second facet to pass through the first facet to a wavelength tuner configured to generate a joint interference spectrum with multiple modes separated by a joint-free-spectral-range (JFSR). Additionally, the method includes configuring the second facet to have reduced reflectivity for increasing wavelengths. Furthermore, the method includes reconfiguring the gain chip with an absorption layer near the active layer to induce a gain loss for wavelengths shorter than a longest wavelength associated with a short-wavelength side mode. Moreover, the method includes outputting amplified light at a basic mode via the second facet.

A light-emitting device includes: a first light source that oscillates in a single lateral mode; a second light source that oscillates in a multiple lateral mode, the second light source having a light output larger than a light output of the first light source and being configured to be driven independently from the first light source; and a light diffusion member that is provided on an emission path of the second light source.

A light emitting element includes a laminated structure formed by laminating a first light reflecting layer 41, a light emitting structure 20, and a second light reflecting layer 42. The light emitting structure 20 is formed by laminating, from the first light reflecting layer side, a first compound semiconductor layer 21, an active layer 23, and a second compound semiconductor layer 22. In the laminated structure 20, at least two light absorbing material layers 51 are formed in parallel to a virtual plane occupied by the active layer 23.

A light-emitting device includes: a light source including light-emitting elements configured to oscillate in a single transverse mode; and an optical member that is provided on a light-emitting path of the light source and configured to diffuse and emit light emitted by the light source.

A method of fabricating an optoelectronic component within a silicon-on-insulator substrate, the method comprising: providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a silicon base layer, a buried oxide (BOX) layer on top of the base layer, and a silicon device layer on top of the BOX layer; etching a first cavity region into the SOI substrate and etching a second cavity region into the SOI substrate, the first cavity region having a first depth and the second cavity region having a second depth, the second depth being greater than the first depth; depositing a multistack epi layer into the first and the second cavity regions simultaneously, the multistack epi layer comprising a first multistack portion comprising a first active region and a second multistack portion comprising a second active region.