A non-planarized VCSEL can include: a blocking region over or under an active region, the blocking region having a first thickness; one or more conductive channel cores in the blocking region, the one or more conductive channel cores having a second thickness that is larger than the first thickness, wherein the blocking region is defined by having an implant and the one or more conductive channel cores are devoid of the implant, wherein the blocking region is lateral the one or more conductive channel cores, the blocking region and one or more conductive channel cores being an isolation region; and a non-planarized semiconductor region of one or more non-planarized semiconductor layers over the isolation region. The VCSEL can include a planarized bottom mirror region below the active region and a non-planarized top mirror region above the isolation region, or a non-planarized bottom mirror region below the active region.

A method for forming a Bragg reflector includes after forming first trenches in the stack, which are intended to form structures of the distributed Bragg reflector, forming a sacrificial interlayer at least in the first trenches, depositing a second masking layer at least inside the first trenches, forming second trenches intended to form sidewalls of the laser, removing the second masking layer from inside the first trenches, removing said sacrificial interlayer so as to remove, by lift-off, residues of the second masking layer that remain inside the first trenches, and filling said first trenches with at least one metal material.

A non-planarized VCSEL can include: a blocking region over or under an active region, the blocking region having a first thickness; one or more conductive channel cores in the blocking region, the one or more conductive channel cores having a second thickness that is larger than the first thickness, wherein the blocking region is defined by having an implant and the one or more conductive channel cores are devoid of the implant, wherein the blocking region is lateral the one or more conductive channel cores, the blocking region and one or more conductive channel cores being an isolation region; and a non-planarized semiconductor region of one or more non-planarized semiconductor layers over the isolation region. The VCSEL can include a planarized bottom mirror region below the active region and a non-planarized top mirror region above the isolation region, or a non-planarized bottom mirror region below the active region.

An etched planarized VCSEL includes: an active region; a blocking region over the active region, and defining apertures therein; and conductive channel cores in the apertures, wherein the conductive channel cores and blocking region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the blocking region over the active region; etching the apertures in the blocking region; and forming the conductive channel cores in the apertures of the blocking region. Another etched planarized VCSEL includes: an active region; a conductive region over the active region, and defining apertures therein; and blocking cores in the apertures, wherein the blocking cores and conductive region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the conductive region over the active region; etching the apertures in the conductive region; and forming the blocking cores in the apertures of the conductive region.

A semiconductor optical integrated device includes: a substrate; at least a lower cladding layer, a waveguide core layer, and an upper cladding layer sequentially layered on the substrate, a buried hetero structure waveguide portion having a waveguide structure in which a semiconductor cladding material is embedded near each of both sides of the waveguide core layer; and a ridge waveguide portion having a waveguide structure in which a semiconductor layer including at least the upper cladding layer protrudes in a mesa shape. Further, a thickness of the upper cladding layer in the buried hetero structure waveguide portion is greater than a thickness of the upper cladding layer in the ridge waveguide portion.

In a semiconductor laser according to an embodiment of the present disclosure, a ridge part has a structure in which a plurality of gain regions and a plurality of Q-switch regions are each disposed alternately with each of separation regions being interposed therebetween in an extending direction of the ridge part. The separation regions each have a separation groove that separates from each other, by a space, the gain region and the Q-switch region adjacent to each other. The separation groove has a bottom surface at a position, in a second semiconductor layer, higher than a part corresponding to a foot of each of both sides of the ridge part. The semiconductor laser includes an electrode provided over the bottom surface of each separation groove with an insulating layer being interposed therebetween.

In a semiconductor laser according to an embodiment of the present disclosure, a ridge part has a structure in which a plurality of gain regions and a plurality of Q-switch regions are each disposed alternately with each of separation regions being interposed therebetween in an extending direction of the ridge part. The separation regions each have a separation groove that separates from each other, by a space, the gain region and the Q-switch region adjacent to each other. The separation groove has a bottom surface at a position, in a second semiconductor layer, higher than a part corresponding to a foot of each of both sides of the ridge part.

A method of fabricating vertical cavity surface emitting laser, comprising: providing a first substrate formed with a dielectric DBR and a first bonding layer, and a second substrate formed with a etch-stop layer, a heavily doped layer, an active region, a current-confinement layer, and an arsenide DBR firstly, then sticking a third substrate on the arsenide DBR, then removing the second substrate and the etch-stop layer, next bonding the heavily doped layer to the dielectric DBR, next removing the third substrate, finally forming a p-type electrode contact and an n-type electrode contact.

A semiconductor optical integrated device includes: a substrate; at least a lower cladding layer, a waveguide core layer, and an upper cladding layer sequentially layered on the substrate, a buried hetero structure waveguide portions each having a waveguide structure in which a semiconductor cladding material is embedded near each of both sides of the waveguide core layer; and a ridge waveguide portion having a waveguide structure in which a semiconductor layer including at least the upper cladding layer protrudes in a mesa shape. Further, a thickness of the upper cladding layer in each of the buried hetero structure waveguide portions is greater than a thickness of the upper cladding layer in the ridge waveguide portion.

Integrated-optics systems are presented in which an optically active device is optically coupled with a silicon waveguide via a passive compound-semiconductor waveguide. In a first region, the passive waveguide and the optically active device collectively define a composite waveguide structure, where the optically active device functions as the central ridge portion of a rib-waveguide structure. The optically active device is configured to control the vertical position of an optical mode in the composite waveguide along its length such that the optical mode is optically coupled into the passive waveguide with low loss. The passive waveguide and the silicon waveguide collectively define a vertical coupler in a second region, where the passive and silicon waveguides are configured to control the distribution of the optical mode along the length of the coupler, thereby enabling the entire mode to transition between the passive and silicon waveguides with low loss.